Samsung Electronics Co., Ltd.

Woosung Choi

Jing Wang

Nuo Xu

Zhengping Jiang

Tae-Kyung Kim

Weiyi Qi

Minji Kim

Hyuk Kang

Dongil Son

Buseop Jung

Jungeun Lee

Yang Lu

Sung-Min Hong

Jooman Han

Jongho Choi

Chihak Ahn

Fan Chen

Yen-kai Lin

Jongchol Kim

Yuanchen Chu

Hong-Hyun Park

Hesameddin Ilatikhameneh

A method includes providing an artificial neural network comprising a compute-in-memory accelerator, the artificial neural network further comprising a hidden layer including a first plurality of artificial neurons; and training the artificial neural network using a bitwise modified rectified linear unit activation function for ones of the first plurality of artificial neurons, the bitwise modified rectified linear unit activation function comprising a bit activation function, which is configured to generate an output that is proportional to an input when the input is less than a critical threshold and configured to generate an output that is independent of the input when the input is greater than the critical threshold, wherein the input comprises a sum, across a second plurality of artificial neurons of a preceding layer of the artificial neural network having a plurality of weights associated therewith, respectively, of a product of an output from a respective one of the second plurality of artificial neurons and one bit of a respective one of the plurality of weights.

Methods of operating an artificial neural network using a compute-in-memory accelerator and a bitwise activation function

A computer implemented method for determining performance of a semiconductor device is provided. The method includes providing training data comprising input state values and training capacitance values to a neural network executing on a computer system; processing the input state values through the neural network to generate modeled charge values; converting the modeled charge values to modeled capacitance values; determining, by the computer system, whether the training capacitance values of the training data are within a threshold value of the modeled capacitance values utilizing a loss function that omits the modeled charge values; and in response to determining that the training capacitance values of the training data are within the threshold value of the modeled capacitance values, converting, by the computer system, the neural network to a circuit simulation code to generate a converted neural network.

Systems, methods, and computer program products for transistor compact modeling using artificial neural networks

A method for generating a model of a transistor includes: initializing hyper-parameters; training the neural network in accordance with the hyper-parameters and training data relating transistor input state values to transistor output state values to compute neural network parameters; determining whether the transistor output state values of the training data match an output of the neural network; porting the neural network to a circuit simulation code to generate a ported neural network; simulating a test circuit using the ported neural network to simulate behavior of a transistor of the test circuit to generate simulation output; determining whether a turnaround time of the generation of the simulation output is satisfactory; in response to determining that the turnaround time is unsatisfactory, re-training the neural network based on updated hyper-parameters; and in response to determining that the turnaround time is satisfactory, outputting the ported neural network as the model of the transistor.

System and method for compact neural network modeling of transistors

A system for reconstructing wafer maps of semiconductor wafers includes: a processor; and memory having instructions stored thereon that, when executed by the processor, cause the processor to: receive test data of a wafer at sparse sampling locations of the wafer, the sparse sampling locations being selected based on a probing mask; and compute a reconstructed wafer map by performing compressed sensing with Zernike polynomials on the test data at sparse locations of the wafer.

Systems and methods for wafer map analysis

A method of manufacturing a p-type MOSFET includes depositing a channel material to form a channel region, forming a source region and a drain region on each side of the channel region along a first direction, depositing a gate oxide layer on the channel region along a second direction crossing the first direction, and depositing a gate electrode on the gate oxide. The channel material includes a group IV element or III-V semiconductor compound and have a diamond or zincblende cubic crystal structure. A &#x3c;001&#x3e; direction of the crystal structure is parallel to the second direction. Two adjacent atoms on an out-most atomic layer of the channel region along the first direction are connected to each other via a single intervening atom, and an interface between the gate oxide layer and the channel region has a surface roughness of 1 angstrom or lower.

Group IV and III-V p-type MOSFET with high hole mobility and method of manufacturing the same

An electronic device providing information through a virtual environment is disclosed. The device includes: a display; and an information providing module functionally connected with the display, wherein the information providing module displays an object corresponding to an external electronic device for the electronic device through the display, obtains information to be output through the external electronic device, and provides contents corresponding to the information in relation to a region, on which the object is displayed.

Virtual environment for sharing information

A method of circuit yield analysis for evaluating rare failure events includes performing initial sampling to detect failed samples respectively located at one or more failure regions in a multi-dimensional parametric space, generating a distribution of failed samples at discrete values along each dimension, identifying the failed samples, performing a transform to project the failed samples into all dimensions in a transform space, and classifying a type of failure region for each dimension in the parametric space.

Generic high-dimensional importance sampling methodology

In a method of circuit yield analysis, the method includes: detecting a plurality of failed samples respectively located at a plurality of failure regions in a multi-dimensional parametric space; clustering the failed samples to identify the failure regions; filtering features of the failed samples to determine a parameter component that is a non-principal component in affecting circuit yield; applying a dimensional reduction method on a dimension corresponding to the parameter component; and constructing a final importance sampling (IS) distribution function using a mixed Gaussian (mGaussian) function corresponding to all of the failure regions containing a rare failure event.

Importance sampling method for multiple failure regions

According to one embodiment of the present invention a circuit simulator configured to simulate a degraded output of a circuit including a plurality of transistors includes: a behavioral recurrent neural network configured to receive an input waveform and to compute a circuit output waveform; a feature engine configured to model one or more degraded circuit elements in accordance with an aging time, to receive the circuit output waveform and to output a plurality of degraded features; and a physics recurrent neural network configured to receive the plurality of degraded features from the feature engine and to simulate the degraded output of the circuit.

System and method for circuit simulation based on recurrent neural networks

A method of circuit yield analysis for evaluating rare failure events existing in multiple disjoint failure regions defined by a multi-dimensional parametric space, the method including performing initial sampling to detect failed samples respectively located at multiple failure regions in the multi-dimensional parametric space, performing clustering to identify the failure regions, performing feature filtering to determine which parameter component is a non-principal component in affecting circuit yield, applying a dimensional reduction method on a dimension corresponding to the parameter component, optimizing an importance sampling (IS) distribution function corresponding to each of the failure regions, and constructing a final importance sampling (IS) distribution function using a mixed Gaussian (mGaussian) function corresponding to all of the failure regions.

A computer implemented method for determining performance of a semiconductor device is provided. The method includes providing a technology computer aided design data set corresponding to nominal performance of the semiconductor device, identifying a plurality of process variation sources that correspond to process variations that occur during the manufacturing of the semiconductor device, generating a nominal value look-up table of electrical parameters of the semiconductor device using nominal values of each of the plurality of process variation sources, and generating a plurality of process variation look-up tables of electrical parameters of the semiconductor device using variation values corresponding to each of the plurality of process variation sources that are identified as corresponding to the semiconductor device.

Systems, methods and computer program products for analyzing performance of semiconductor devices

A method for selecting transistor design parameters. A first set of simulations is used to calculate leakage current at a plurality of sets of design parameter values, and the results are fitted with a first response surface methodology model. The first model is used to generate a function that returns a value of a selected design parameter, for which a leakage current specification is just met. A second set of simulations is used to calculate effective drive current for a plurality of sets of design parameter values, and the results are fitted with a second response surface methodology model. The second model is used, together with the first, to search for a set of design parameter values at which a worst-case effective drive current is greatest, subject to the constraint of meeting the worst-case leakage current specification.

Method for transistor design with considerations of process, voltage and temperature variations

Neural signal amplifiers include an operational amplifier and a feedback network coupled between an output and an input thereof. The feedback network includes a tunnel field effect transistor ('TFET') pseudo resistor that exhibits bi-directional conductivity. A drain region of the TFET may be electrically connected to the gate electrode thereof to provide a bi-directional resistor having good symmetry in terms of resistance as a function of voltage polarity.

Amplifiers including tunable tunnel field effect transistor pseudo resistors and related devices

A method and electronic device for processing an image in an electronic device. The method includes predicting the number of surfaces which can be partitioned in image data; determining an inverse distortion rendering method corresponding to the predicted number of surfaces as a method for inverse distortion rendering of the image data; rendering the image data to a distorted image based on the determined inverse distortion rendering method; and displaying the distorted image.

Inverse distortion rendering method based on a predicted number of surfaces in image data

Tunnel field effect transistors include a semiconductor substrate; a source region in the semiconductor substrate; a drain region in the semiconductor substrate; a channel region in the semiconductor substrate between the source region and the drain region; and a gate electrode on the semiconductor substrate above the channel region. The source region comprises a first region having a first conductivity type, a third region having a second conductivity type that is different from the first conductivity type, and a second region having an intrinsic conductivity type that is between the first region and the third region.

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Pleasanton, CA, United States of America

Woosung Choi