Samsung Electronics Co., Ltd.

Woosik Kim

Hokyu Kang

Seungheon Song

Heedon Jeong

Sangyoon Kim

Jongmil Youn

Je-min Yoo

Hwasung Rhee

A semiconductor device includes a substrate with a NMOS region and a PMOS region, a device isolation layer on the substrate to define active fins, and gate patterns on the substrate to have a length direction crossing the active fins, wherein the device isolation layer includes diffusion brake regions between respective pairs of the active fins, the diffusion brake regions being disposed adjacent to each other in a width direction of the gate patterns, and wherein a width of the diffusion brake region in the NMOS region is different from a width of the diffusion brake region in the PMOS region.

Semiconductor device with fin field effect transistors

Semiconductor device with fin field effect transistors having different separation regions between fins in NMOS and PMOS regions

A Scalable Two-Transistor Memory (STTM) cell array having a 4F unit cell area, where F is the minimum feature size. The data lines and the bit lines alternate and are adjacent to each other along the Y-axis direction, and the word lines are laid out along the X-axis direction. Each STTM cell consists of a floating gate MOS sensing transistor at the surface of a semiconductor substrate, with a vertical double sidewall gate multiple tunnel junction barrier programming MOS transistor on top of the sensing transistor. A data line connects all source regions of the programming transistors and a bit line connects all the source/drain regions of the sensing transistors in a column direction. A word line connects all double sidewall gate regions of programming transistors in a row direction. This invention also deals with a column addressing circuit as well as the driving method for the circuit.

Scalable two transistor memory device

A method of fabricating a multiple tunnel junction Scalable Two-Transistor Memory (STTM) cell array with a unit cell area as low as 4F , F representing the minimum feature dimension, which usually is the width and also the spacing of the data lines or the write (or word or control gate) lines, wherein process sequence and conditions are designed to offer wide flexibility in material choices and layer thickness at different regions of the STTM cell with surface planarity maintained at several stages of the manufacturing sequence. The processing of memory cell devices is made compatible with peripheral CMOS devices so that the devices in both areas can be made simultaneously, thereby decreasing the total number of processing steps. Insulator filled trenches around the device regions, source/drain and the gate regions of the peripheral devices are formed simultaneously with the corresponding regions of the memory cell devices.

Method of making a scalable two transistor memory device

Growing community of inventors

Suwon, South Korea

Woosik Kim