Samsung Electronics Co., Ltd.

Wooseop Kim

Chanik Park

Insu Choi

Dae-Jeong Kim

Sung-Joon Kim

Wonjae Shin

Tae-Kyeong Ko

Yongjun Yu

Jungjoon Lee

Dongmin Jang

Jongyoung Lee

Jiseok Kang

Hui-Chung Byun

Seon-Sik Kim

Changwoo Koo

A memory system includes a nonvolatile memory module and a first controller configured to control the nonvolatile memory module. The nonvolatile memory module includes a volatile memory device, a nonvolatile memory device, and a second controller configured to control the volatile memory device and the nonvolatile memory device. The first controller may be configured to transmit a read request to the second controller. When, during a read operation according to the read request, normal data is not received from the nonvolatile memory device, the first controller may perform one or more retransmits of the read request to the second controller without a limitation on a number of times that the first controller performs the one or more retransmits of the read request.

Memory system including memory module, memory module, and operating method of memory module

A memory system includes a processor that includes cores and a memory controller, and a first semiconductor memory module that communicates with the memory controller. The cores receive a call to perform a first exception handling in response to detection of a first error when the memory controller reads first data from the first semiconductor memory module. A first monarchy core of the cores performs the first exception handling and the remaining cores of the cores return to remaining operations previously performed.

Memory systems and operating methods of memory systems

A semiconductor module includes: a module board, a plurality of chips mounted on the module board, and a plurality of array resistors mounted on the module board, the plurality of array resistors including at least a first array resistor. The first array resistor may include a substrate comprising a top surface, a bottom surface opposite the top surface, and first to fourth side surfaces connecting the top surface to the bottom surface, the first and third side surfaces being opposite each other, and the second and fourth side surfaces being opposite each other; a plurality of first electrodes disposed on the first side surface of the substrate, each first electrode including at least a first portion on the first side surface of the substrate and a second portion on the bottom surface of the substrate; a plurality of second electrodes disposed on the third side surface of the substrate, each second electrode opposite a respective first electrode and including at least a first portion on the third side surface of the substrate and a second portion on the bottom surface of the substrate; for each pair of respective first and second electrodes opposite each other, a resistor disposed on the substrate between the respective first and second electrodes; and at least one third electrode disposed on the second side surface of the substrate, the third electrode including at least a first portion on the second side surface of the substrate and a second portion on the bottom surface of the substrate. Each of the first electrodes, the second electrodes, and the third electrode may be bonded to the module board.

Array resistor and semiconductor module

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Seoul, South Korea

Wooseop Kim