Samsung Electronics Co., Ltd.

WooSeong Cheong

Kyungeun Choi

Daehyun Kim

Dae-Ho Kim

Seonghoon Woo

Chanho Yoon

Bumseok Yu

Kiman Choo

Jaehwan Yu

Changhoon Han

Jaechun Park

Provided are a memory system and an operating method of the memory system. The memory system includes a memory controller configured to generate a first command and a second command in response to receiving a sequential command from a host, and a first memory device and a second memory device each configured to receive the first command and the second command, wherein the sequential command is a command to determine or indicates whether to access each of the first memory device and the second memory device, and the memory controller is further configured to determine whether to access at least one memory device among the first and second memory devices, transmit the first command to the first memory device when the first memory device is to be accessed, and transmit the second command to the second memory device when the second memory device is not to be accessed.

Memory system and memory controller that transmits commands to memory devices and operating method thereof

An electronic system includes a plurality of master devices, a memory controller and a memory device. The master devices generate requests for memory access operations, where each request includes locality information indicating whether requests are to be executed continuously. The memory controller receives the requests from the plurality of master devices, determines an execution order of the requests based on the locality information, and sequentially generates commands to perform the memory access operations according to the execution order. The memory device receives the commands from the memory controller and performs the memory access operations based on the commands.

Memory controller, system, and method of scheduling memory access execution order based on locality information

An operating method of a storage device is provided. The operating method includes: receiving a host read command from a host device; identifying whether a read path corresponding to the host read command corresponds to a first direct memory access (DMA) read path; and directly outputting, by a host DMA manager, read data stored in an output buffer of an error correction circuit to the host device based on the read path corresponding to the first DMA read path.

Controller controlling non-volatile memory device, storage device including the same, and operating method thereof

In a method of scheduling commands for a memory device including a plurality of storage regions, a plurality of host commands used to access the plurality of storage regions are received from a host device. The plurality of host commands are queued in a first command queue. A first scheduling associated with the plurality of host commands is performed based on a mapping table and operation states of the plurality of storage regions. The mapping table includes a correspondence between the plurality of host commands and the plurality of storage regions. The plurality of host commands are executed based on a result of the first scheduling. In response to a bank collision occurring while the plurality of host commands are executed, a second scheduling associated with the plurality of host commands is performed.

Method of scheduling commands for memory device and memory system performing the same

A storage device includes a non-volatile memory including a plurality of non-volatile memory cells, a buffer memory configured to temporarily store write data to be written to the non-volatile memory or read data read from the non-volatile memory, and a controller configured to receive a sleep mode signal from an external host. When the sleep mode signal is received by the controller, the controller is configured to block a first power supplied to the non-volatile memory and set the buffer memory to one of a first mode in which a second power is blocked from being supplied to the buffer memory and a second mode in which the buffer memory operates with low power. The write data stored in the buffer memory is written to the non-volatile memory when the buffer memory is set to the first mode.

Data and power management of partitioned buffer in a storage device

Buffer management during power state transitions using self-refresh and dump modes

A storage device includes a controller and a nonvolatile memory device. The controller includes a field programmable gate array (FPGA) and receives an FPGA image for updating the FPGA from an outside in response to a first command received from the outside. The nonvolatile memory device stores the FPGA image. The controller receives the FPGA image through a main interface or a sideband interface, and executes the FPGA image in response to a second command received from the outside.

Storage device configured to update field programmable gate array and method of operating the same

A non-signal analyzing method for a data storage system including a storage device connected to a host via a data line and a power line includes; communicating a non-signal from the host to the storage device via the power line, detecting the non-signal in the storage device and return the non-signal through to the host via the data line, and analyzing the returned non-signal using a protocol analyzer to generate analysis results characterizing the returned non-signal.

Data storage system and method analyzing non-signal

At least one example embodiment discloses a method of managing a power between a host serial advanced technology attachment (SATA) interface and a device SATA interface. The method includes first requesting to enter one of power saving states, defined by a SATA protocol, and second requesting to enter a deep power saving state if one of the host SATA interface and the device SATA interface operates at the first requested power saving state. The first requesting to enter one of power saving states and the second requesting to enter a deep power saving state are performed by one of the host SATA interface and the device SATA interface.

Serial advanced technology attachment interfaces and methods for power management thereof

A memory controller includes first and second interface controllers configured to exchange data with external devices, and an internal block connected between the first and second interface controllers. The first and second interface controllers exchange data received from the external devices and at least one parity bit corresponding to the received data through the internal block.

Growing community of inventors

Suwon-si, South Korea

WooSeong Cheong