Samsung Electronics Co., Ltd.

Wooseok Kim

Wonsik Yu

Chanyoung Jeong

Taeik Kim

Kangyeop Choo

Jusung Lee

Jihyun Kim

Insung Kim

Dokyung Lim

Eunsung Seo

Jisu Yu

Noyoung Chung

Sangdon Jung

Joomyoung Kim

Byung Je Jung

Youngsook Do

Sounghun Shin

Youngwoo Jo

Hyunik Kim

Sunghyuck Lee

A semiconductor device includes: a standard cell array including a plurality of standard cells, each of the plurality of standard cells; a plurality of power supply lines configured to provide a power supply voltage and extending in a first direction; a capacitor structure including electrode structures included in each of a plurality of dielectric layers formed on the standard cell array, the capacitor structure having vias connecting the electrode structures; and contacts electrically connecting the capacitor structure and the standard cell array to each other. Each of the plurality of standard cells provides a unit capacitor circuit having capacitance that is based on a connection structure of active regions and gates of first and second transistors thereof.

Semiconductor devices and methods of manufacturing the same

A method includes grouping, in a first layout, pattern regions which have duplicate layout patterns including weak regions as a group, calculating defect probabilities of the pattern regions, respectively, calculating a defect frequency and a defect rate of the group based on the defect probabilities of the pattern regions, predicting a degree of defects of a second layout of the pattern regions, based on the defect frequency and the defect rate, and performing an extreme ultraviolet (EUV) lithography process on a substrate, based on the second layout. The defect probabilities are calculated by performing an optical proximity correction (OPC) simulation on the pattern region, calculating a stochastic variation of a linewidth of a simulation pattern in the weak region as a Gaussian distribution, and defining a threshold linewidth, which is used as a reference of the random defect, in the Gaussian distribution.

Lithography and method of fabricating semiconductor device using the same

A phase-locked loop device and its operating method are provided. The phase-locked loop device includes a voltage controlled oscillator configured to generate an output clock signal, a divider configured to divide the output clock signal into first and second phase division signals having a constant phase difference, a sampling phase frequency detector configured to sample a sampling voltage based on the first phase division signal and output any one of the sampling voltage, a first supply voltage, and a second supply voltage based on the second phase division signal, a transconductance circuit configured to output a conversion current based on a hold voltage, and a loop filter configured to generate a voltage control signal based on the conversion current and output the voltage control signal to the voltage controlled oscillator.

Phase-locked loop device and operation method thereof

An electronic device including: a regulator circuit configured to output a regulated voltage based on a reference voltage and a feedback voltage; and an oscillator configured to generate an output frequency signal based on a reference frequency signal and the regulated voltage output from the regulator circuit, wherein the regulator circuit includes: a feedback loop configured to output the regulated voltage based on a difference between the reference voltage and the feedback voltage; a first capacitor; a precharge circuit connected to the feedback loop, and configured to charge the first capacitor with a second voltage which is based on a first voltage; a first switch configured to connect the precharge circuit with the first capacitor; and a second switch configured to connect the first capacitor with the feedback loop.

Regulator circuit, an electronic device including the regulator circuit, and a processor including the regulator circuit

A monitoring circuit for a high frequency signal includes: a phase locked loop configured to generate a divided output signal with respect to an input signal based on a plurality of dividers; a plurality of dividing monitoring circuits configured to receive dividing input signals and dividing output signals respectively corresponding to the plurality of dividers, and output dividing error signals; and a jitter monitoring circuit configured to output a jitter error signal.

Monitoring circuit of phase locked loop and operating method thereof

A frequency-locked loop (FLL) logic circuit, including a validity signal generator configured to receive an external clock signal and determine whether a glitch occurs in the external clock signal; a clock divider configured to generate a reference frequency clock signal based on the external clock signal and a determination result of the validity signal generator; a synchronizer configured to synchronize a phase of an oscillator clock signal with a phase of the reference frequency clock signal; a clock counter configured to count a number of pulses of the oscillator clock signal during a reference time; and a code limiter configured to determine a range of a frequency selection value for calibrating an operating frequency of the oscillator clock signal based on the counted number of pulses.

Oscillation system including frequency-locked loop logic circuit and operating method thereof

A bandgap reference circuit includes a reference current generation circuit configured to output a bandgap reference current insensitive to a temperature change, by using a first voltage inversely proportional to temperature and a third voltage proportional to temperature. The third voltage is a difference between the first voltage and a second voltage. The bandgap reference circuit further includes a resistivity temperature coefficient cancellation circuit configured to remove a first current proportional to temperature from the bandgap reference current by using the third voltage, and a reference voltage generation circuit configured to output a bandgap reference voltage insensitive to a temperature change by using a second current inversely proportional to temperature and a first resistance proportional to temperature. The second current is generated by removing the first current from the bandgap reference current.

Bandgap reference circuit including resistivity temperature coefficient cancellation circuit, and oscillator circuit including the bandgap reference circuit

A digitally controlled oscillator (DCO) includes; a current mirror configured to generate a supply current in response to a bias voltage matching a reference current, a variable resistor connected to the current mirror through a first node outputting the reference current and configured to provide a variable resistance in response to a first control signal, an oscillation circuit connected to the current mirror through a second node outputting the supply current and configured to generate an oscillation signal in response to the supply current, and a feedback circuit configured to control the bias voltage in relation to at least one of a voltage at the first node and a voltage at the second node.

Digitally controlled oscillator insensitive to changes in process, voltage, temperature and digital phase locked loop including same

A phased locked loop includes; a load circuit that generates an output signal in response to a driving voltage, a frequency calibration circuit that generates a calibration signal in response to an output frequency of the output signal and a target frequency, and a regulator that generates the driving voltage in response to the calibration signal.

Phase locked loop generating adaptive driving voltage and related operating method

A temperature compensated oscillation controller includes a temperature compensation circuit configured to provide a reference voltage through a first terminal and to receive an input voltage including temperature information through a second terminal, and an oscillation circuit configured to be connected to an external crystal resonator through third and fourth terminals and to output a clock signal in response to an oscillation signal from the external crystal resonator. The temperature compensation circuit is configured to perform a voltage controlled oscillator-based sensing operation to convert the input voltage into a temperature code and to adjust a frequency of the clock signal using the temperature code.

Temperature compensated oscillation controller and temperature compensated crystal oscillator including the same

A digital phase locked loop circuit includes a phase frequency detector, a bandwidth calibrator, a digital loop filter, and a digital controlled oscillator. The phase frequency detector generates a first detection value and a second detection value of which each is associated with order between a phase of a reference signal and a phase of a fed-back signal. The bandwidth calibrator amplifies a signal level of the second detection value by a gain value to generate an amplified detection value, and adjusts the gain value based on the first detection value. The digital loop filter generates a digital code based on the amplified detection value. The digital controlled oscillator generates an output signal having a frequency which corresponds to the digital code. The fed-back signal is generated based on the output signal and is fed back to the phase frequency detector.

Digital phase locked loop circuit adjusting digital gain to maintain loop bandwidth uniformly

A digital phase locked loop includes a digital phase detector, a digital loop filter, a digital controlled oscillator, a first divider that divides the second frequency of the oscillation signal depending on a first division value and outputs the division result as a division signal having a third frequency, a second divider that divides the second frequency of the oscillation signal depending on a second division value and outputs the division result as an output signal having a final frequency, a dithering block that receives the division signal and performs dithering on the first division value based on a preset pattern as cycles of the division signal pass, and a digital phase domain filter that performs second low pass filtering on the division signal in a phase domain and outputs the result of the second low pass filtering as the feedback signal.

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Suwon-si, South Korea

Wooseok Kim