Samsung Electronics Co., Ltd.

Samsung Display Co., Ltd.

Woonkyung Lee

Sunil Shim

Jaehoon Jang

Wonseok Cho

Kihyun Hwang

Hansoo Kim

Byeong-In Choe

Kihyun Kim

Sung-Min Hwang

Seung-jun Lee

Jaeyoung Ahn

Jung-Hwan Lee

Sunggil Kim

Bonyoung Koo

Jin-Kyu Kang

Jeeyong Kim

Jintae Noh

Byoungsun Ju

Jin-Sung Lee

Phil Ouk Nam

Jaegoo Lee

Jin-Soo Lim

Juyul Lee

Junkyu Yang

Chaeho Kim

Hui-Chang Moon

Jongsik Chun

Jin-Yong Oh

Juhyung Kim

Wookhyoung Lee

Kyoung-Hoon Kim

Jungdal Choi

Jintaek Park

Jae-Joo Shim

Hoosung Cho

Changseok Kang

Byong-Hyun Jang

Sung-Hwan Jang

Jong-Yeon Kim

Byong-hyun Jang

A semiconductor device includes a plurality of first insulating layers and a plurality of second layers alternately and vertically stacked on a substrate. Each of the plurality of second layers includes a horizontal electrode horizontally separated by a second insulating layer. A contact plug penetrates the plurality of first insulating layers and the second insulating layer of the plurality of second layers.

Semiconductor devices and methods of fabricating the same

A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.

Semiconductor memory devices and methods of fabricating the same

Provided is a semiconductor device including gate structures provided on a substrate, a separation insulating layer interposed between the gate structures, and a plurality of cell pillars connected to the substrate through each gate structure. Each gate structure may include horizontal electrodes vertically stacked on the substrate, and an interval between adjacent ones of the cell pillars is non-uniform.

Semiconductor device having staggered pillars

A nonvolatile memory device includes a substrate and a plurality of cell strings provided on the substrate, each cell string including a plurality of memory cells stacked in a direction perpendicular to the substrate. The methods may include applying a word line erase voltage to word lines connected to memory cells of the cell strings; floating ground selection lines connected to ground selection transistors of the cell strings and string selection lines connected to string selection transistors of the plurality of cell strings; applying a ground voltage to at least one lower dummy word line connected to at least one lower dummy memory cell between memory cells and a ground selection transistor in each of the plurality of cell strings; applying an erase voltage to the substrate; and floating the at least one lower dummy word line after applying of the erase voltage.

Operating methods of nonvolatile memory devices including a ground select transistor and first and second dummy memory cells

Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.

Semiconductor devices

A three-dimensional semiconductor device includes a substrate having a cell array region between first and second contact regions. A first stack includes a plurality of first electrodes vertically provided on the substrate, and a second stack includes a plurality of second electrodes vertically provided on the first stack. The second stack is arranged to expose end portions of the first electrodes on the first contact region and overlap end portions of the first electrodes on the second contact region.

Three-dimensional semiconductor device

Semiconductor device

Methods of operating a nonvolatile memory device may include applying a word line erase voltage to word lines connected to memory cells of the plurality of cell strings, floating ground selection lines connected to ground selection transistors of the plurality of cell strings and string selection lines connected to string selection transistors of the plurality of cell strings, applying a ground voltage to at least one lower dummy word line connected to at least one lower dummy memory cell between memory cells and a ground selection transistor in each of the plurality of cell strings, applying an erase voltage to the substrate, and floating the at least one lower dummy word line after applying of the erase voltage.

Erasing methods of three-dimensional nonvolatile memory devices with cell strings and dummy word lines

A three dimensional semiconductor memory device has a stacked structure including cell gates stacked therein that are insulated from each other and first string selection gates laterally separated from each other, vertical active patterns extending through the first string selection gates, multi-layered dielectric layers between sidewalls of the vertical active patterns and the cell gates and between the sidewalls of the vertical active patterns and the first string selection gates, and at least one first supplement conductive pattern. The first string selection gates are disposed over an uppermost cell gate of the cell gates. Each vertical active pattern extends through each of the cell gates stacked under the first string selection gates. The first supplement conductive pattern is in contact with a sidewall of one of the first string selection gates.

Methods of fabricating three dimensional semiconductor memory devices

Three-dimensional semiconductor devices may be provided. The devices may include a stack-structure including gate patterns and an insulation pattern. The stack-structure may further include a first portion and a second portion, and the second portion of the stack-structure may have a narrower width than the first portion. The devices may also include an active pattern that penetrates the stack-structure. The devices may further include a common source region adjacent the stack-structure. The devices may additionally include a strapping contact plug on the common source region.

Three-dimensional semiconductor devices

A nonvolatile memory device includes a substrate, a structure including a stack of alternately disposed layers of conductive and insulation materials disposed on the substrate, a plurality of pillars extending through the structure in a direction perpendicular to the substrate and into contact with the substrate, and information storage films interposed between the layers of conductive material and the pillars. In one embodiment, upper portions of the pillars located at the same level as an upper layer of the conductive material have structures that are different from lower portions of the pillars. In another embodiment, or in addition, upper string selection transistors constituted by portions of the pillars at the level of an upper layer of the conductive material are programmed differently from lower string selection transistors.

Nonvolatile memory device and method of making the same

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Seongnam-si, South Korea

Woonkyung Lee