Samsung Electronics Co., Ltd.

Woonhyuk Choi

Noyoung Chung

Akio Misaka

Sangwoo Park

Sanghwa Lee

Taekyum Kim

Jungkee Choi

A layout method of a semiconductor chip, includes designing a layout using a restriction rule such that a layout pattern having a length smaller than a first length in a first direction has to have a length smaller than a second length in a second direction, the second direction intersecting the first direction, generating a plurality of unit regions by partitioning the layout in the first direction, generating a plurality of target regions by adding a reference region to a partitioned edge of each of the plurality of unit regions, retargeting the plurality of target regions in parallel, and generating a correction layout by merging the plurality of retargeted target regions.

Layout method of semiconductor chip, semiconductor chip manufacturing method and computing device using same

A semiconductor device may include a metal pattern in a device region of a substrate, and a macro pattern structure in a scribe lane region of the substrate. The macro pattern structure may include a plurality of types of macro patterns. Each type of macro pattern may include a color 1 pattern and a color 2 pattern adjacent to the color 1 pattern. The color 1 pattern and the color 2 pattern may include conductive lines extending in a first direction parallel to a surface of the substrate. The color 1 pattern and color 2 pattern may be alternately arranged in a second direction perpendicular to the first direction and parallel to the surface of the substrate.

Semiconductor device including a macro pattern structure for monitoring of line widths

A method of manufacturing a semiconductor device includes randomly placing a plurality of standard cells from a library in which the standard cells are pre-stored, designing an interconnection pattern in which the standard cells are connected randomly to each other, connecting the standard cells according to the interconnection pattern to generate a virtual layout, performing an optical proximity correction operation on the virtual layout using an optical proximity correction (OPC) model, and forming and verifying a mask corresponding to the virtual layout on which the optical proximity correction operation is performed.

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Hwaseong-si, South Korea

Woonhyuk Choi