Skhynix Inc.

Woongrae Kim

Chul Moon Jung

Kyung Mook Kim

Sangkwon Lee

Seung Hun Lee

Tae Yong Lee

Geun Ho Choi

Tae-Yong Lee

Yoonna Oh

Byeong Yong Go

Bok Rim Ko

Yoo-Jong Lee

A-Ram Rim

Keun Soo Song

Myung Kyun Kwak

Se Won Lee

Sang Il Park

Seung Wook Oh

Jeong Tae Hwang

Byeong Cheol Lee

Kwi Dong Kim

Jong-Hyun Park

Jung-Hyun Kim

Sang Sic Yoon

Saeng Hwan Kim

Hoiju Chung

Jeong-Tae Hwang

Da In Im

Young Jun Yoon

Duck Hwa Hong

Jong Seok Han

Sang-Kwon Lee

A Ram Rim

Yoo Jong Lee

Yeonsu Jang

Mi-Hyun Hwang

Jung Min Yoon

Sang Woo Yoon

Do Hong Kim

Woo Jin Kang

Jong-Ho Son

Uk Song Kang

A memory system includes: a memory controller suitable for generating a first target address by sampling an address according to an active command, and providing the active command, a precharge command, a normal refresh command, the address and the first target address, to a memory device; and the memory device suitable for generating a first target refresh command according to the precharge command and the address, and refreshing one or more word lines corresponding to the first target address according to the first target refresh command.

Semiconductor memory device performing target refresh and memory system including the same

A memory device includes: a rate control circuit configured to: generate a refresh counting value based on a refresh management command and an internal target refresh command, and generate a rate control signal by comparing the refresh counting value with a target value corresponding to temperature information; and a target command issuing circuit configured to: set a target number according to the rate control signal, and issue the internal target refresh command whenever a number of inputs of a normal refresh command reaches the target number.

Memory device and memory system for performing target refresh operation, and operation method thereof

A memory device includes a sense amplifying circuit coupled between a pull-up voltage line and a pull-down voltage line and configured to sense and amplify data of bit lines according to a sensing control signal; a fail detection circuit configured to calculate counting values of fail bits for each temperature based on the data and configured to generate a minimum error code for each temperature by detecting a minimum value for each temperature from the counting values for each temperature, in response to a test mode signal; and a sense amplifying control circuit configured to drive the pull-up voltage line and the pull-down voltage line by generating a pull-up voltage and a pull-down voltage corresponding to current temperature information based on the minimum error code for each temperature and configured to generate the sensing control signal according to the test mode signal.

Memory device including sense amplifying circuit

A semiconductor memory device includes: a memory cell region including normal cells and row-hammer cells coupled to each of a plurality of rows, wherein the row-hammer cells of a selected row are suitable for storing first data and second data, the first data representing a number of accesses to the selected row and the second data denoting whether to refresh second adjacent rows of the selected row; and a refresh control circuit suitable for: selecting a sampling address based on the first data read from a row corresponding to an input address when an active command is inputted, determining, in response to a refresh command, whether to refresh first adjacent rows of a target row corresponding to the sampling address, and determining, in response to the refresh command, whether to refresh second adjacent rows of the target row based on the second data read from the target row.

Memory device and operating method for target refresh operation based on number of accesses

A semiconductor memory device includes: a memory cell region including a plurality of cell mats in each of which a plurality of rows are disposed, each row coupled to normal cells and row-hammer cells; a repair control circuit suitable for generating a pairing flag denoting whether a cell mat in which an active row corresponding to an active address is disposed, is repaired with another cell mat; and a refresh control circuit suitable for: selecting, when an active command is inputted, a sampling address based on first and second data read from the row-hammer cells of the active row, refreshing, when a target refresh command is inputted, one or more adjacent rows to a target row corresponding to the sampling address, and selectively refreshing, when the target refresh command is inputted, one or more adjacent rows to a paired row of the target row according to the pairing flag.

Semiconductor memory device and operating method thereof

An operation method of a memory may include entering a self-refresh mode, increasing a level of a back-bias voltage in response to entering the self-refresh mode, performing self-refresh operations in a first cycle, confirming that the back-bias voltage reaches a level of a first threshold voltage, and performing the self-refresh operations in a second cycle longer than the first cycle in response to the confirmation.

Memory and operation method thereof

A memory includes: a memory core; a list storage circuit suitable for storing a weak row list of rows that are vulnerable to a row hammer attack in the memory core; and a row hammer attack detection circuit suitable for selecting rows that are row-hammer-attacked among rows in the memory core as hammered rows, and increasing a probability that the rows stored in the list storage circuit are selected as the hammered rows.

Memory with row hammer mitigation technique

A method for operating a memory includes: receiving an active command and a row address; confirming that a portion of columns of a first row corresponding to the row address is replaced with a portion of columns of a second row; activating the first row and the second row; confirming activation of a random pulse; randomly selecting one among the row address corresponding to the first row and a row address corresponding to the second row in response to the activation of the random pulse; and sampling the selected row address as a sampling address.

Memory and operation method of memory with repairing and random pulse generating capability

An integrated circuit includes: first and second pattern generation circuits generating first and second pattern signal for a sampling section; a first section control part generating a coarse section signal for a first section of the sampling section, according to the first pattern signal; a first filter part generating a first section extract signal by filtering the second pattern signal according to the coarse section signal; a second section control part generating a fine section signal for a second section of the sampling section, according to the first section extract signal; a second filter part generating a second section extract signal by filtering the second pattern signal according to the fine section signal; an output control circuit generating a sampling enable signal according to the first and second section extract signals; and a sampling circuit suitable for sampling an input signal according to the sampling enable signal.

Integrated circuit and memory device including sampling circuit

A memory device may include: a memory region including a plurality of word lines, a self-refresh command generation circuit suitable for generating self-refresh commands for each predetermined interval during a self-refresh period, a refresh check circuit suitable for generating a ratio signal by checking a ratio which word lines refreshed in response to the self-refresh commands occupy among the plurality of word lines, a ratio adjustment circuit suitable for adjusting, among a plurality of auto-refresh commands inputted from an external device during an auto-refresh period, a ratio of to-be-applied commands, which are to be used for a refresh operation, to to-be-skipped commands, which are to be skipped for the refresh operation, according to the ratio signal, and a refresh operation circuit suitable for performing the refresh operation on the plurality of word lines in response to the self-refresh commands and the to-be-applied commands.

Apparatus and method for controlling refresh operation

A memory device includes: a refresh control circuit configured to generate a self-refresh command and a refresh address, word line control circuits configured to control a refresh operation of a plurality of word lines, a group management circuit configured to classify N address groups by grouping the refresh addresses to be generated by the refresh control circuit and to select from the N address groups, a current address group including a refresh address to be currently generated and a subsequent address group including a refresh address to be generated after the current address group according to the predetermined order, a row control circuit configured to group the plurality of word line control circuits with N control signals respectively corresponding to the N address groups, respectively, and a supply control circuit configured to activate signals corresponding to the current and subsequent address groups among the N control signals.

Apparatus and method for controlling supply of power for refresh operation

A memory device may include: a memory bank comprising a plurality of memory blocks, each divided into a normal area and a row hammer area, a command control circuit suitable for performing an access operation on the normal area in response to an active command, an internal command generation circuit suitable for generating an internal command in response to a precharge command, a target address generation circuit suitable for saving a count for each logic level combination of a received address in the row hammer area by performing an access operation on the row hammer area in response to the internal command, and setting an address corresponding to the count as a target address when the count satisfies a preset condition, and a refresh control circuit suitable for controlling a smart refresh operation on the target address.

Memory device for performing smart refresh operation by counting received address

A method for operating a memory system includes: collecting, by a memory controller, information on rows that are determined as row-hammer-attacked in a memory by the memory controller; collecting, by the memory, information on rows that are determined as row-hammer-attacked by the memory; confirming, by the memory, that the row collected by the memory controller is the same as the row collected by the memory; and resetting, by the memory, information on the row collected by the memory which is the same as the row collected by the memory controller in response to the confirmation.

Memory, memory system and operation method of memory system

A memory system includes: an address scrambler suitable for scrambling an address based on a scrambling rule to generate a scrambled address; a memory core including a plurality of memory cells and suitable for storing data in memory cells designated by the scrambled address; and a scramble control circuit suitable for changing the scrambling rule in response to satisfaction of an attack condition.

Memory system and operation method of memory system

Growing community of inventors

Icheon-si, South Korea

Woongrae Kim