Samsung Electronics Co., Ltd.

Korea Advanced Institute of Science and Technology

Seoul National University

Snu Rdb Foundation

Woong Seo

Soo-Jung Ryu

Young-chul Cho

Yeon-Gon Cho

John Dongjun Kim

Soojung Ryu

Ho-Young Kim

Yeongon Cho

Moo-Kyoung Chung

Jeongae Park

Il-hyun Park

Yoon-Jin Kim

Tae-Wook Oh

Seok-Woo Song

Min-Seok Lee

Sangheon Lee

Santosh Abraham

Dong-Hoon Yoo

Bernhard Egger

Jin-Seok Lee

Karthik Ramani

Kiyoung Choi

Kwontaek Kwon

Seunghun Jin

Han-Joon Kim

Sang Heon Lee

Jinho Lee

Jae-Young Kim

Jaejin Lee

Ho Young Kim

Seong Hoon Jeong

Seok Hyun Kang

Namhyung Kim

Soo-jung Ryu

Sung-Bae Park

Jeong-Wook Kim

Hee-jun Shim

Changmoo Kim

Yen-Jo Han

Seung-Hun Jin

Young-Chul Cho

Minseok Lee

Chang-Moo Kim

Junwhan Ahn

Choon-Ki Jang

Sun Min Kwon

Hee Jun Shim

Sungju Han

Il-Hyun Park

A swizzle pattern generator is provided to reduce an overhead due to execution of a swizzle instruction in vector processing. The swizzle pattern generator is configured to provide swizzle patterns with respect to data sets of at least one vector register or vector processing unit. The swizzle pattern generator may be reconfigurable to generate various swizzle patterns for different vector operations.

Processing device and a swizzle pattern generator

A graphics processing unit (GPU), configured to perform tile-based rendering using prefetched graphics data, includes a tiler configured to perform binning on a current frame and obtain a first binning bitstream of a first tile among a plurality of tiles of the current frame, a binning correlator configured to determine whether the first tile and a second tile of a previous frame are similar to each other by using the first binning bitstream and a second binning bitstream of the second tile, where the second tile has a same tile ID as the first tile, a prefetcher configured to prefetch second graphics data used to render the second tile by using the tile ID, when it is determined that the first tile and the second tile are similar to each other, and at least one processor configured to render the current frame using the prefetched second graphics data.

Apparatus and method for performing tile-based rendering using prefetched graphics data

An apparatus and a job scheduling method are provided. For example, the apparatus is a multi-core processing apparatus. The apparatus and method minimize performance degradation of a core caused by sharing resources by dynamically managing a maximum number of jobs assigned to each core of the apparatus. The apparatus includes at least one core including an active cycle counting unit configured to store a number of active cycles and a stall cycle counting unit configured to store a number of stall cycles and a job scheduler configured to assign at least one job to each of the at least one core, based on the number of active cycles and the number of stall cycles. When the ratio of the number of stall cycles to a number of active cycles for a core is too great, the job scheduler assigns fewer jobs to that core to improve performance.

Job scheduling optimization based on ratio of stall to active cycles

A method of managing graphics data in a graphics processing device may include: receiving a first draw call having a first identifier, generating a first lookup table having the first identifier mapped in association with a first handle value by allocating the first handle value to the first identifier, generating a second lookup table having the first handle value mapped in association with a first graphics state setting value by allocating the first handle value to the first graphics state setting value, wherein the first graphics state setting value corresponds to the first identifier, and performing at least one graphics pipeline operation to process the first draw call by using the first graphics state setting value obtained from the second lookup table.

Methods and apparatuses for managing graphics data using two-stage lookup tables in cache

A texture processor includes: a texture cache configured to store textures; a controller configured to determine a texture address corresponding to a requested texture among the stored textures and read a texture corresponding to the texture address from the texture cache; a format converter configured to convert a format of the read texture into another format, based on a degree of texture precision required by a graphics processing unit (GPU); and a texture filter configured to perform texture filtering using the read texture having its format converted into the another format.

Texture processing apparatus and method

Provided is a multi network and method to transmit packets. The multi network includes a mesh network, a tree network, and a network interface connected to the mesh network and the tree network and configured to transmit, through the mesh network and the tree network, a packet generated by a processing unit, of a processing system having plural processing units, at a starting point to a destination point for another processing unit of the processing system and configured to selectively inject the packet into one of the mesh network and the tree network to transmit the packet to the other processing unit.

Apparatus and method transmitting packets

A method of managing a cache includes storing first data of an upper level cache in a lower level cache, predicting a reuse distance level of second data having a same signature as the first data based on access information about the first data, and storing the second data in one of the lower level cache and a main memory based on the predicted reuse distance level of the second data.

Computing apparatus and method for cache management

Provided is a processor including a plurality of devices. The processor includes a source processing device configured to identify data to request from another device, and a destination processing device configured to, in response to a request for the identified data from the source processing device using credit-based flow control, transmit the identified data to the source processing device using the credit-based flow control. The source processing device includes a credit buffer used for the credit-based flow control, the credit buffer being allocable to include a cache region configured to cache the transmitted identified data received by the source processing device.

Processor and method

A texture cache architecture includes a first texture cache to store compressed texel data and a second texture cache to store decompressed texel data. A controller schedules accesses to access texel data from the first or second texture cache. The second texture cache permits decompressed texel data to be reused for more than one texel access request.

Efficient low-power texture cache architecture

A method of executing a graphics pipeline includes calculating, while executing the graphics pipeline on a current frame, a resource for processing properties of an object included in a following frame, determining, based on a result of the calculating, whether to perform a pre-process for the object included in the following frame, performing the pre-processing, when the pre-process is determined to be performed, comprising transforming the properties of the object that are to be processed in a graphics pipeline for the following frame, and executing, when the pre-process is to be performed, the graphics pipeline for the following frame by using the transformed properties of the object.

Method and apparatus for executing graphics pipeline

Embodiments include a processor capable of supporting multi-mode and corresponding methods. The processor includes front end units, a number of processing elements more than a number of the front end units; and a controller configured to determine if thread divergence occurs due to conditional branching. If there is thread divergence, the processor may set control information to control processing elements using currently activated front end units. If there is not, the processor may set control information to control processing elements using a currently activated front end unit.

Processor and method for dynamically allocating processing elements to front end units using a plurality of registers

A texture cache architecture facilitates access of compressed texture data in non-power of two formats, such as the Adaptive Scalable Texture Compression (ASTC) codec. In one implementation, the texture cache architecture includes a controller, a first buffer, a second buffer, and a texture decompressor. A first buffer stores one or more blocks of compressed texel data fetched, in response to a first request, from a first texture cache, where the one or more blocks of compressed texel data including at least requested texel data. The second buffer stores decompressed one or more blocks of compressed texel data and provides the decompressed requested texel data as output to a second texture cache. The one or more blocks of compressed texel data stored by the first buffer includes second texel data in addition to the requested texel data.

Cache architecture for efficiently accessing texture data using buffers

A cache memory and a method of managing the same are provided. The method of managing a cache memory includes determining whether a number of bits of a data bandwidth stored in a bank is an integer multiple of a number of bits of unit data in data to be stored, storing first unit data, among the data to be stored, in a first region of a first address in the bank in response to the number of bits of the data bandwidth not being the integer multiple of the number of bits of the unit data, and storing part of second unit data, among the data to be stored, in a second region of the first address.

Cache memory and method of managing the same

A processor and corresponding method are described including cores having a thread set allocated based on a pre-set implementation order, and a controller configured to receive scheduling information determined based on an implementation pattern regarding the allocated thread set from one of the cores and transmit the scheduling information to another of the cores. The one of cores determines the scheduling information according to characteristics of an application when implementation of the thread set is completed. Each of the cores re-determines an implementation order regarding the allocated thread set based on the determined scheduling information.

Method and processor for implementing thread and recording medium thereof

A tile-based rendering method includes performing binning of a current frame; generating an identification code of binning information or property information of a tile to be rendered in the current frame; comparing the identification code of the tile to be rendered to an identification code of a previous tile, wherein a location of the previous tile in a previous frame is the same as a location of the tile to be rendered in the current frame; and rendering the current frame by either re-using an image stored in a frame buffer or performing pixel processing of the tile to be rendered depending on a result of the comparing.

Tile-based rendering apparatus and method for rendering 3D graphics using binning information and property information

Growing community of inventors

Hwaseong-si, South Korea

Woong Seo