Samsung Electronics Co., Ltd.

Korea University Research and Business Foundation

Skhynix Inc.

Hynix Semiconductor Inc.

Egtm Co., Ltd.

Woong Il Choi

Jongsun Park

Yong-wan Jin

Do-yeon Kim

Kyeongho Lee

Kyung-bae Park

Jong Sun Park

Kyu-sik Kim

Kwang-hee Lee

Bulliard Xavier

Do-hwan Kim

Sun-kook Kim

Sung-Jin Cho

Suk Bae Kim

Ji Eun Jun

Su Hwan Ji

Yong Wan Jin

Kyung Bae Park

Jae-young Choi

Jong Hoon Kim

Kwang Hee Lee

Geun Su Lee

Sang-Yoon Lee

Jung Won Lee

Do Hwan Kim

Taejoong Song

Ha Na Kim

Kyu Sik Kim

Hyun Mun Kim

Tae-sang Kim

Dong Hyun Lee

Jae Min Kim

Do-Yeon Kim

Eun Ae Jung

Soo-Ghang Ihn

Young Bog Kim

Woojin Rim

Jae Man Yoon

Gyuhong Kim

Byoung Do Lee

Eung-ryeol Seo

Hong-Yeol Lee

Jae Hyun Son

Sung-young Yun

Kuk Jin Chun

Geon-ung Lee

Myung Soo Lee

Ji Won Moon

Woo Jun Lee

Jun-hong Park

Dae Sung Cho

Hyun Sik Noh

Jong-ha Park

Kwanghyo Jeong

Dae Hee Kim

Bong Soo Jung

Jang Hee Ryu

Kwang Pyo Choi

Dong Hak Jang

Geon Ko

Yun Seok Chun

A washing machine and a method for controlling the same are provided. The washing machine includes a first rotary tub, a first driver configured to rotate the first rotary tub, a second rotary tub, a second driver configured to rotate the second rotary tub, and at least one processor configured to control the first driver and the second driver in a manner that the first rotary tub and the second rotary tub rotate. If a rotation speed of the first rotary tub is equal to or higher than a first reference speed, the at least one processor controls the second driver such that a rotation speed of the second rotary tub increases to a target speed and then decreases.

Washing machine and method for controlling the same

An in-memory computing device includes a memory cell array and a column peripheral circuit including a plurality of column peripheral units connected to a plurality of pairs of bit lines connected to the memory cell array. Each of the column peripheral units includes a sense amplifying and writing unit sensing and amplifying bitwise data through one pair of bit lines among the pairs of bit lines and an arithmetic logic unit performing an arithmetic operation with a full adder Boolean equation based on the bitwise data and performing a write back operation on operation data obtained by the arithmetic operation via the sense amplifying and writing unit.

In-memory computing device supporting arithmetic operations

A computing in-memory device includes a memory cell array supporting a bitwise operation through at least one pair of memory cells activated in response to at least one pair of word line signals and a peripheral circuit connected to the at least one pair of memory cells via one pair of bit lines and performing a discharging operation on at least one bit line of the one pair of bit lines based on a voltage level of the one pair of bit lines.

Computing in-memory device supporting arithmetic operations and method of controlling the same

Disclosed are an artificial neural network device and a method of operating the same. The artificial neural network device includes an operation part performing an artificial neural network operation on an input feature map and a classification part performing a classifying operation on the input feature map based on the artificial neural network operation of the operation part. The operation part includes an XNOR operation circuit performing an XNOR operation on the input feature map and a filter and a binarizing circuit performing a binarization operation based on the result of the XNOR operation of the XNOR operation circuit. Accordingly, the artificial neural network device is miniaturized and performs the operation at high speed.

Processor in memory supporting binary convolution operation and method of operating the same

Disclosed is a method of forming a thin film using a surface protection material, the method comprising supplying the surface protection material to the inside of a chamber on which a substrate is placed so that the surface protection material is adsorbed to the substrate, discharging the unadsorbed surface protection material from the inside of the chamber by purging the interior of the chamber, supplying a metal precursor to the inside of the chamber so that the metal precursor is adsorbed to the substrate, discharging the unadsorbed metal precursor from the inside of the chamber by purging the interior of the chamber, and supplying a reaction material to the inside of the chamber so that the reaction material reacts with the adsorbed metal precursor to form the thin film.

Method of forming a thin film using a surface protection material

Disclosed is a washing machine having an improved structure so as to enable noise reduction. The disclosed washing machine comprises: a main body; a drum rotatably disposed inside the main body; and a detergent supply device provided in the main body and supplying detergent into the drum, wherein the detergent supply device includes: a housing; a detergent container containing the detergent and movably coupled to the housing; and a water supply frame having an inflow hole through which water supplied from the outside flows in, and a flow velocity mitigation part provided at the lower side of the inflow hole so as to mitigate the flow velocity of the water.

Detergent supply device and washing machine including same

A CAM device includes a cell array including a plurality of CAM cells, a search line driving circuit connected to the cell array through a plurality of search lines, and a match line sensing circuit connected to the cell array through a plurality of match lines. Each of the CAM cells includes a first half CAM cell connected to a first match line and a second half CAM cell connected to a second match line different from the first match line. The first match line connected to the first half CAM cell is precharged in a first phase, and the second match line connected to the second half CAM cell is precharged in a second phase after the first phase. Thus, power consumption of the CAM device is reduced and delay is minimized.

Content addressable memory device with charge sharing based selective match line precharging scheme

A method for SRAM yield estimation includes: generating a first perturbation vector depending on a DC voltage input condition for an assist operation section of a SRAM which is an estimation target; calculating a first margin on the basis of the first perturbation vector; performing an AC simulation during the assist operation section depending on the DC voltage input condition; generating a second perturbation vector depending on a DC voltage input condition for a normal operation section which is set when the AC simulation is ended; calculating a second margin on the basis of the second perturbation vector; and selecting a minimum margin from among the first margin and the second margin and estimating a yield of the SRAM on the basis of the selected margin.

Method for SRAM yield estimation

Provided is a device configured to perform a convolution operation. The device includes bi-directional First In First Out memory including bi-directional latches configured to transfer data in a first direction or a second direction depending on a clock signal and connected to each other and performs a convolution operation of an input value and a filter. The device stores first input values corresponding to a window equivalent to a size of the filter from a input value matrix in the bi-directional First In First Out memory in response to a first convolution operation and stores second input values corresponding to a location of the window which is moved in the first direction or the second direction by a predetermined amount from locations of the first input values in the bi-directional First In First Out memory in response to a second convolution operation subsequent to the first convolution operation.

Bi-directional FIFO memory and convolution processing device using the same

An electronic device is provided. The electronic device includes a camera configured to obtain an image, an input buffer configured to store the image, an encoder implemented with hardware, and configured to encode an image output from the input buffer, at least one memory, and a processor configured to electrically connect with the camera, the input buffer, the encoder, and the at least one memory. The processor is configured to generate an encoding parameter based on a characteristic of the encoder receiving the encoding parameter and to provide the encoding parameter to the encoder.

Electronic device and image encoding method of electronic device

Provided is a pixel of a multi-stacked complementary metal-oxide semiconductor (CMOS) image sensor and a method of manufacturing the image sensor including a light-receiving unit that may include first through third photodiode layers that are sequentially stacked, an integrated circuit (IC) that is formed below the light-receiving unit, electrode layers that are formed on and below each of the first through third photodiode layers, and a contact plug that connects the electrode layer formed below each of the first through third photodiode layers with a transistor of the IC.

Pixel of a multi-stacked CMOS image sensor and method of manufacturing the same

The digital signal processor includes a DRAM including multiple memory cells configured to store data in a parasitic capacitor and a core logic configured to perform an operation of recording, reading, or updating data in the DRAM on the basis of a predetermined digital signal processing architecture. The core logic: records input data in a memory cell of the DRAM; reads the recorded input data before a retention time passes; and externally outputs the data or stores the data in another memory cell of the DRAM.

Systems and methods for processing data

A semiconductor device includes a bit line disposed over a semiconductor substrate, a supporting film being perpendicular to the bit line, a first storage node contact disposed at a lower part of a region disposed between the bit line and the supporting film, and a second storage node contact having a line shape, disposed over the first storage node contact and the bit line, isolated by the supporting film, and patterned in a diagonal direction across the bit line.

Semiconductor device and method for fabricating the same

A memory device includes a first memory cell array including memory cells of a single-ended bitline structure, a second memory cell array including memory cells of a single-ended bitline structure, a reference voltage generator configured to output a bitline voltage of a selected one of the first and second memory cell arrays as a sensing voltage according to an array select signal and output a bitline voltage of an unselected memory cell array as a reference voltage, and a differential sense amplifier configured to amplify and output a difference between the sensing voltage and the reference voltage. Logic states of the sensing voltage and the reference voltage are complementary to each other.

Memory device of a single-ended bitline structure including reference voltage generator

Growing community of inventors

Osan-si, South Korea

Woong Il Choi