Samsung Electronics Co., Ltd.

Korea Electrotechnology Research Institute

Woon-Yong Park

Dong-Gyu Kim

Jong-Soo Yoon

Sang-Soo Kim

Dong-gyu Kim

Mun-Pyo Hong

Il-Gon Kim

Hyeon-Hwan Kim

Sahng-Ik Jun

Young-Mi Tak

Bum-Ki Baek

Yu-Ri Song

Joo-Hyung Lee

Jong-Woong Chang

Dong-Hyeon Ki

In-sik Jang

Jun-ho Song

Jang-Soo Kim

Byoung-Sun Na

Seung-Soo Baek

Jun-Ho Song

Young-Sun Kim

Jin-Oh Kwag

Cheol-Soo Jung

Ho-Joon Lee

Yeong-Hwan Cho

Bung-Hyuk Min

Seog-Chae Lee

Chang-Oh Jeong

Jung-Ho Lee

Won-hee Lee

Jung-Hee Lee

Kwon-Young Choi

Myung-Jae Park

Kyung-seop Kim

Kyung-nam Lee

Shi-yual Kim

Sang-Ki Kwak

Haeng-Won Park

Yoan Shin

Sungsoo Choi

Young-Jae Tak

Kyeong-Nam Lee

Kyuha Chung

Seung-Taek Lim

Jin-Kwan Kim

You-Lee Song

Joong-hee Lee

Won Cheol Lee

Kwan-Ho Kim

Yong-guk Pae

Hui-Myung Oh

Youngjin Park

A data line and an amorphous silicon pattern are formed on a substrate. The first electrode pattern is extended from the data line and overlaps an edge of the amorphous silicon pattern. The second electrode pattern is made of the same metal as the first electrode pattern and overlaps the edge of the amorphous silicon pattern at an opposite side of the first electrode pattern. Edges of the first and the second electrode patterns are sharply formed so that a tunneling effect easily occurs through the amorphous silicon pattern. An indium-tin-oxide pattern for a capacitor is formed at the end of the second electrode pattern. The capacitor is formed between the ITO pattern and a common electrode.

Thin film transistor array panel

The invention is directed to simultaneously etching thin films to different uniform depths depending on positions by using a photoresist pattern having different thickness depending on positions as an etch mask in order to form a contact hole for a gate pad along with at least one other layer, or a data wire and a semiconductor pattern, via a single photolithography step.

Thin film transistor array panels for a liquid crystal display and a method for manufacturing the same

A thin film transistor (TFT) array panel that includes a substrate, a gate wire including a gate pad, a gate insulating layer pattern, a semiconductor layer pattern, an ohmic contact layer pattern, a data wire including a data pad and a drain electrode, and a passivation layer pattern is presented. The passivation layer pattern is formed on the data wire and has contact holes exposing the gate pad, the data pad, and the drain electrode. The passivation layer pattern also has a planar shape that is similar that of the semiconductor layer pattern due to simultaneous etching except for the portions adjoining the drain electrode and the data pad, having a width greater than that of the data wire, and covering a boundary line of the data wire. A pixel electrode is electrically connected to the exposed portion of the drain electrode and contacts the gate insulating layer pattern.

Method for manufacturing a thin film transistor array panel for a liquid crystal display and a photolithography method for fabricating thin films

A passivation layer is deposited and a photoresist is formed. The photoresist includes first to third portions with decreased thickness, the second portions located on portions of drain electrodes and data lines and the third portions located on portions of gate lines. A mask for forming the photoresist has rectilinear slits with width and distance of about 0.8-2.0 microns on an area corresponding to the second portions. The passivation layer and an underlying semiconductor layer as well as the photoresist are etched to expose portions of the gate insulating layer under the third portions of the photoresist as well as portions of the passivation layer under the second portions of the photoresist. The exposed portions of the passivation layer and the gate insulating layer are removed to expose the drain electrodes, the gate lines and the data lines as well as portions of the semiconductor layer, which are subsequently removed.

Thin film transistor array panel, manufacturing method thereof, and mask therefor

A thin film transistor (TFT) array panel that includes a substrate, a gate wire formed on the substrate, a gate insulating layer pattern formed on the gate wire, a semiconductor layer pattern formed on the gate insulating layer pattern, an ohmic contact layer pattern formed on the semiconductor layer pattern, a data wire formed on the ohmic contact layer pattern, a passivation layer pattern formed on the data wire, and a pixel electrode is presented. The data wire includes a data pad. The ohmic contact layer pattern includes a portion disposed under the data pad that is simultaneously etched as the data pad, and a contact hole in the passivation layer is etched simultaneously as a contact hole in the gate insulating layer.

The present invention relates to a liquid crystal display having repair lines and methods of repairing defect in the same. The liquid crystal display comprises a plurality of gate lines in horizontal direction, a plurality of data lines perpendicular thereto, and a plurality of repair lines repeatedly formed corresponding to a fixed number of data lines. The repair line comprises an upper portion crossing top of the data lines, a lower portion crossing bottom of the data lines, and a middle portion which is parallel to the data line connecting the upper and the lower portions. A repair line is formed repeatedly for each data-line block which consists of data lines in any multiples of three. Under the above wiring structure, a disconnected data line is repaired by shorting the crossing points of the data line and the repair line corresponding to the data-line block of the disconnected data line.

LCD having repair lines wherein first and second signal lines include means for receiving the same gate signal thereon are formed on a TFT insulating substrate

A method of fabricating a thin film transistor array substrate for a liquid crystal display includes the step of forming a gate line assembly with gate lines, gate electrodes and gate pads. After laying a plurality of layers on the substrate, a photoresist film is deposited onto the layers. The photoresist film is first exposed to light at a first light exposing unit, and secondly exposed to light at a second light exposing unit such that the photoresist film has three portions of different thickness. The photoresist pattern, and some of the underlying layers are etched to form a data line assembly, a semiconductor pattern, and an ohmic contact pattern. The data line assembly includes data lines, source and drain electrodes, and data pads. The remaining photoresist film is removed, and a protective layer is formed on the substrate. The protective layer is etched together with the gate insulating layer to form first to third contact holes exposing the drain electrode, the gate pad and the data pad, respectively. Pixel electrodes, subsidiary gate and data pads are then formed.

Photolithography method for fabricating thin film

Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched. After depositing a passivation layer, a opening is formed by using the fourth mask and the exposed semiconductor layer through the opening is etched to separate the semiconductor layer under the adjacent data line.

Thin film transistor array panel for a liquid crystal display and a method for manufacturing the same

A plurality of gate lines and a plurality of data lines intersecting each other are formed on a first insulating substrate having a plurality of first cutouts are formed on the respective pixel areas defined by the data lines and the gate lines. A thin film transistor is connected to each pixel electrode. A reference electrode having a plurality of second cutouts is formed on a second substrate opposite the first substrate. The first cutouts and the second cutouts in the adjacent two pixel areas opposite each other with respect to one data line have an inversion symmetry with respect to the data line.

Vertically aligned mode liquid crystal display

A gate line is formed on a substrate in a horizontal direction and a data repair line is formed on the same layer as the gate line in a vertical direction. The repair line is divided into two portions with respect to the gate line. A gate insulating film is formed on the gate line and the data repair line, and a data line is formed on the gate insulating film along the repair line having a smaller width than the repair line, a passivation film being deposited thereon. Contact holes are formed in the passivation film, and contact holes to expose both ends of the divided repair line are formed in the passivation film and gate insulating film. A transparent connecting pattern formed on the passivation film contacts the data line and the repair line through the contact holes. Both ends of the repair line are extended from the data line. A pixel electrode is formed on the passivation film, and the pixel electrode overlaps the edges of the repair line at a predetermined width. The repair line functions as a signal transmitting path when the data line is disconnected, and as a black matrix for blocking light-leakage. The transparent connecting pattern acts as a path when the data line is disconnected at the portion where the gate line intersects the data line.

Liquid crystal display

Disclosed is a wireless positioning system and method that can perform a high-precision position tracking. The wireless positioning system includes a target device that is an object of wireless positioning, beacon devices and a processing unit. The beacon devices transmits wireless signals and sense reception time points of the wireless signals transmitted from the other beacon devices and the target device and received at time points after the transmission of the wireless signal. The target device receives the wireless signal transmitted from at least one of the beacon devices, and then transmits the wireless signal to the beacon devices. The processing unit obtains the position of the target device by calculating distances between the beacon devices and the target device using information about the reception time points of the wireless signals sensed by the respective beacon devices.

System and method for asynchronous wireless positioning by ordered transmission

A thin film transistor array substrate for a liquid crystal display includes an insulating substrate with a display area and a peripheral area surrounding the display area. The peripheral area has an upper region above the display area and a lower region below the display area. Signal lines are formed on the substrate such that the signal lines are bundled into a plurality of blocks. Each block has a predetermined number of signal lines. A plurality of first upper repair lines is formed at the upper peripheral region of the substrate, crossing one or more blocks of the signal lines. A plurality of second upper repair lines is formed at the upper peripheral region of the substrate, crossing all of the signal lines. A plurality of first lower repair lines are formed at the lower peripheral region of the substrate, connected to the corresponding first upper repair lines. The first lower repair lines cross the signal lines crossed by the first upper repair lines. A plurality of second lower repair lines is formed at the lower peripheral region of the substrate, crossing all of the signal lines. A plurality of upper connection members crosses the first upper repair lines and the second upper repair lines. A plurality of lower connection members crosses the first lower repair lines and the second lower repair lines. In this structure, even though line breakage is concentrated at a particular area, such line breakage can be collectively repaired using the spare neighboring repair lines and interconnection lines interconnecting the repair lines efficiently.

Thin film display transistor array substrate for a liquid crystal display having repair lines

A gate line extending in a horizontal direction is formed on an insulating substrate, and a data line is formed perpendicular to the gate line defining a pixel of a matrix array. Pixel electrodes receiving image signals through the data line are formed in a pixel, and a thin film transistor having a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode is formed on the portion where the gate lines and the data lines intersect. A storage wire including a storage electrode line in the horizontal direction, a storage electrode connected to the storage electrode line, and at least one of the storage electrode connection portions connecting storage electrodes of neighboring pixels is formed in the same direction as the gate line. A redundant repair line overlaps and is insulated from the storage wire at one end and overlaps the storage wire or the gate wire of a neighboring pixel at the other end is formed in the same layer as the data wire. Also, a storage wire connection portion connecting the storage wires of a neighboring pixel is formed in the same layer as the pixel electrode. In this structure, if portions of the gate wire or the data wire are disconnected, the portions overlapping the disconnected wire, the storage wire, and the redundant repair line are shorted to repair an open wire defect.

A matrix-type display device having a repair layout, particularly, a matrix-type display device which can be repaired in a pixel unit, is provided. Two or more of signal lines such as scanning signal lines, displaying signal lines and auxiliary signal lines and a pixel electrode are overlapped via an insulating layer, so that a defect such as the disconnection of the displaying signal lines and scanning signal lines, the short of the pixel electrode and signal line, and the loss of electrode of a switching element, can be repaired. Here, the layout of the auxiliary gate line and dual gate line can be modified.

Matrix-type display device capable of being repaired in pixel unit

Growing community of inventors

Suwon, South Korea

Woon-Yong Park