Samsung Display Co., Ltd.

Woon Yong Lim

Ki Hyun Pyun

Sung Soo Choi

Young Uk Hwang

Tong Ill Kwak

Bong Kyun Jo

A converter includes a phase locked loop ('PLL') unit which outputs a first frequency signal having a first frequency during a first period of one frame and to output a second frequency signal modulated to have a frequency corresponding to a pattern of an image signal during a second period other than the first period, a pulse width modulation ('PWM') signal generator which generates a PWM signal according to the frequency of the frequency signal outputted from the PLL unit, and a voltage generator which outputs a driving voltage obtained by modulating an input voltage in response to the PWM signal to a voltage output terminal.

Converter and display apparatus including the same

An exemplary embodiment of present disclosure provides a display device including a first horizontal line, a first delay line, a second delay line, a delay value determiner, and a timing controller. The first horizontal line receives a gate pulse signal (CPV) generated by a gate driver. The first delay line is connected to the first horizontal line to transmit a gate pulse signal received at a first horizontal position as a first delay signal. The second delay line is connected to the first horizontal line to transmit a gate pulse signal received at a second horizontal position as a second delay signal. The delay value determiner generates a horizontal delay signal based on the first delay signal and the second delay signal. The timing controller determines generation times of line latch signals applied to a plurality of data lines based on the horizontal delay signal.

Display device and driving method thereof

An image correcting unit including: a data converting unit which receives image data, and generates display data by converting respective grayscale values which are included in the image data to high pixel data and low pixel data; and a white pixel detecting unit which detects image data lines which include not less than a first number of white grayscale values from the image data, and outputs a conversion signal when not less than a second number of the detected image data lines are successively arranged, wherein upon receiving the conversion signal from the white pixel detecting unit, the data converting unit converts the white grayscale values which are included in the successively arranged image data lines to first high pixel data and first low pixel data, wherein the first high pixel data and the first low pixel data have a different value from each other.

Image correcting unit and a liquid crystal display device having the same

A display device includes a display unit including a light emitting device, data and gate driver for respectively applying data and gate voltages to the display unit, and a signal controller for transmitting, to the data driver, image data having a clock embedded therein. The data driver recovers a first internal reference clock during a low period of a first frame control signal, using the image data having the clock embedded therein, compares the frequency of the recovered first internal reference clock with the frequency of a previously stored reference clock, when the frequency of the recovered first internal reference clock is within an error range of the frequency of the previously stored reference clock, outputs the recovered first internal reference clock and receives a second frame control signal, and when the second frame control signal corresponds to a CDR unit operating condition, recovers a second internal reference clock.

Growing community of inventors

Yongin-si, South Korea

Woon Yong Lim