Google Inc.

Woon Seong Kwon

Teckgyu Kang

Nam Hoon Kim

Ryohei Urata

Madhusudan K Iyengar

Hong Liu

Yuan Hang Li

Mikhail Popovich

Gregory Sizikov

Jorge Padilla

Houle Gan

William F Edwards

Yujeong Shim

Richard Roy

Pierre-Luc Cantin

Erick Tuttle

Phillip La

Michael Trent Wise

The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.

Backside integrated voltage regulator for integrated circuits

Integrated circuit substrates having features for containing liquid adhesive, and methods for fabricating such substrates, are provided. A device can include a first substrate layer and a second substrate layer adhered to the first substrate layer such that a portion of the top surface of the first substrate layer is exposed to define a bottom of a cavity, and an edge of the second substrate layer adjacent to the exposed top surface of the first substrate layer defines an edge of the cavity. The device can include an integrated circuit die adhered to the exposed top surface of first substrate layer with a liquid adhesive. The first substrate layer can define a trench in the bottom of the cavity between a region of the integrated circuit die and the edge of the cavity such that the trench can receive bleed-out of the liquid adhesive from between the integrated circuit die and the top surface of the first substrate layer.

Integrated circuit substrate for containing liquid adhesive bleed-out

A packaged assembly and a method of producing the packaged assembly is disclosed. The packaged assembly includes a redistribution layer (RDL), an integrated circuit (IC), one or more memory modules, and an interposer comprising a plurality of vias from a list of through-silicon-vias (TSVs), through-mold-via (TMVs), and plated-through-hold-via (PTHs). In some implementations, the IC is electrically and mechanically attached to a first side of the RDL. In some implementations, the one or more memory modules and the interposer are disposed on a second side of the RDL. The packaged assembly also includes a mold having a mold material encapsulating the IC, the one or more memory modules, the interposer, and the RDL to form the packaged assembly. In some implementations, the IC is electrically conductively connected an external circuit board via a series of electrical connections between the IC, the RDL, the vias, and the external circuit board.

Wafer level fan-out application specific integrated circuit bridge memory stack

A processor assembly and a system including a processor assembly are disclosed. The processor assembly includes an interposer disposed on a substrate, an integrated circuit disposed on the interposer, a memory circuit disposed on the interposer and coupled to the integrated circuit, and a capacitor embedded in the interposer. The capacitor includes at least a first non-planar conductor structure and a second non-planar conductor structure separated by a non-planar dielectric structure. The capacitor includes a first capacitor terminal electrically coupling the first non-planar conductor structure to a first voltage terminal in the integrated circuit. The capacitor includes a second capacitor terminal electrically coupling the second non-planar conductor structure to a second voltage terminal in the integrated circuit. The capacitor includes an oxide layer electrically isolating the capacitor from the interposer.

Massive deep trench capacitor die fill for high performance application specific integrated circuit (ASIC) applications

Integrated component packages and methods of assembling integrated component packages are provided. The integrated component package can comprise a bump pitch relaxing layer. A high-bandwidth memory component directly mechanically coupled to the bump pitch relaxing layer on a first side of the bump pitch relaxing layer via a first set of bump bond connections. The high-bandwidth memory component directly electrically coupled to the bump pitch relaxing layer on the first side of the bump pitch relaxing layer via the first set of bump bond connections. The bump pitch relaxing layer mechanically coupled to a first side of a substrate via second set of bump bond connections. The high-bandwidth memory component electrically coupled to the substrate via the bump-pitch relaxing layer and the second set of bump bond connections, and a bump pitch of the second set of bump bond connections is larger than the first set of bump bond connections.

High bandwidth memory package for high performance processors

A stiffener apparatus for reducing warpage of an integrated circuit package during heating and cooling are provided. The stiffener apparatus includes an IC substrate configured to receive an IC die on a top side of the IC substrate. The stiffener apparatus includes a primary stiffener ring adhered to the top side of the IC substrate and defining an opening in a region of the IC die such that the primary stiffener ring surrounds the region of the IC die. The primary stiffener ring defines a plurality of grooves. The stiffener apparatus includes a secondary stiffener ring having a plurality of catches configured to engage with the plurality of grooves to removably attach the secondary stiffener ring to the primary stiffener ring on a side of the primary stiffener ring opposite the IC substrate. A method of using a stiffener apparatus during a manufacturing operation is also provided.

Apparatus and mechanisms for reducing warpage and increasing surface mount technology yields in high performance integrated circuit packages

Embedded air gap transmission lines and methods of fabrication are provided. An apparatus having an air gap transmission line can include a first conductive plane, a core dielectric layer having a bottom surface in contact with the first conductive plane, a conductor having a bottom surface in contact with a top surface of the core dielectric layer, and a second conductive plane positioned over, and spaced apart from, a top surface of the conductor such that a gap separates the conductor from the second conductive plane. The top surface of the conductor is separated from the bottom surface of the second conductive plane by a first distance measured along an axis normal to the first conductive plane, and the bottom surface of the conductor is separated from the first conductive plane by a second distance greater than the first distance measured along the axis.

Embedded air gap transmission lines

The subject matter of this specification generally relates to electronic packages. In some implementations, a lidless electronic package includes a substrate having a surface and a die disposed on the surface of the substrate. The die has an outside perimeter, a bottom surface adjacent to the surface of the substrate, and a top surface. The electronic package includes a stiffener disposed on the surface of the substrate. The stiffener includes a first surface that is a first distance from the surface of the substrate and a second surface disposed between the die and the first surface. The first distance is greater than a distance between the surface of the substrate and the top surface of the die. The second surface is a second distance from the surface of the substrate that is less than the distance between the surface of the substrate and the top surface of the die.

Package stiffener for protecting semiconductor die

Signal integrity in high-speed applications is dependent on both the underlying device performance and electronic packaging methods. The maturity of chip-on-board (COB) packaging technology using wire bonding makes it a cost beneficial option for the mass production of high-speed optical transceivers. However, wire bonding introduces parasitic inductance associated with the length of the bond wires that limits the scalability of the system for higher data throughput. A high-speed optical transceiver package according to a first proposed configuration minimizes packaging related parasitic inductance by vertically integrating components using flip-chip bonding. A high-speed optical transceiver package according to a second proposed configuration minimizes packaging related parasitic inductance with horizontal tiling of components using a chip carrier and flip-chip bonding.

Integration of silicon photonics IC for high data rate

An IC package is configured to receive a voltage regulator and a load. The IC package includes a plurality of buildup layers disposed on a plurality of core layers. The buildup layers have a top side that includes first and second surface features for receiving the voltage regulator and the load, respectively. First and second pluralities of vias connect the first and second surface features, respectively, to a buildup conductor layer and a core conductor layer. The buildup conductor layer includes a substantially solid or continuous conductor plane extending across and connected to the first and second pluralities of vias. The buildup conductor layer defines a gap between the first and second pluralities of vias, the gap partially separating a portion of the conductor plane connected to the first plurality of vias from a portion connected to the second plurality of vias.

Growing community of inventors

Cupertino, CA, United States of America

Woon Seong Kwon