Electronics and Telecommunications Research Institute

Korea Telecommunication Authority

Woon-Seob So

Do-Young Kim

Byung-Sun Lee

Dae-Hwan Hwang

Hyun-Joo Bae

Jin-Tae Kim

Bong-Tae Kim

Young-Sun Kim

Seung-Han Choi

A fixed mobile convergence terminal using a wideband voice codec is provided. The fixed mobile convergence terminal includes a communication unit configured to connect to a network, and a control unit configured to download a wideband voice codec identical to a wideband voice codec of an opposite party terminal from a call control server in a call setting with the opposite party terminal through the communication unit, so that a high-quality voice call function is achieved.

Fixed mobile convergence terminal using downloadable wideband voice codec, method thereof and method of providing wideband voice codec in call control server

An Internet Set-Top Box (ISTB) and a method of providing wideband IP telephony services using the ISTB are provided, which are capable of implementing wideband voice communication services using a wideband voice codec, controlling a Real-Time Transport Protocol (RTP) packet payload to process a variety of wideband speech frame payloads, and providing high-quality wideband IP telephony services by controlling a jitter buffer to maintain conference call synchronization.

Set-top box for wideband IP telephony service and method for providing wideband IP telephony service using set-top box

Provided is an apparatus for developing and verifying a system-on-chip for an Internet phone. The object of the present invention is to provide the system-on-chip developing and verifying apparatus for the Internet phone, which can develop and verify the system-on-chip simultaneously by integrating an Advanced RISC Machine(ARM) core module, a field programmable gate array (FPGA), a peripheral interface and the system-on-chip. The apparatus includes an ARM core module performing a core processor function, a peripheral interface including a memory and many external input/output devices, a FPGA controlling the ARM core module and performing a control function for connecting the ARM core module and the peripheral interface, and a system-on-chip integrating the functions of the ARM core module and the FPGA.

Apparatus for developing and verifying system-on-chip for internet phone

Disclosed is a communication terminal for a wire and wireless network phone which comprises: a communication service controller, including a RISC processor, for processing protocols that satisfy respective communication interfaces in hardware and software manners; a reset unit for applying a reset signal to be used for the communication service controller; a clock signal unit for supplying clock signals needed for the communication service controller; a memory connected to the communication service controller, for storing a start program, a terminal management program, user data, and various application programs; and an access unit for providing a VoIP telephone function, a DSL access function, an analog telephone function, an Ethernet access function, a wireless network access function, and an EIA232 access function.

Communication terminal for wire and wireless internet phone

The present invention is directed to a system-on-chip development apparatus for wire/wireless Internet telephone. The system-on-chip development apparatus for wire/wireless Internet telephone according to the present invention adds functions indispensable to a RISC core, constructs a core kernel section using a device integrating additional FPGAs available to support additional functions, and provides a plurality of interfaces necessary to an Internet telephone function centering around the core kernel section. With this, the number of necessary component parts can be minimized to facilitate design and simplify the configuration thereof.

System-on-chip development apparatus for wire and wireless internet phone

A dual port random access memory (RAM) matching circuit for a Versa Module Europe bus (VMEbus) which makes it possible to have a higher capacity when transmitting and receiving data by using a RAM which is possible to bidirectionally access during a communication between processors using a VMEbus of an electronic switching system. The dual port RAM matching circuit includes a dual port RAM for bidirectionally outputting/inputting a data in accordance with an address and a control signal, an address matching unit for selecting first through sixteenth addresses from a local system or first through sixteenth addresses from a VMEbus in accordance with the control signal, and a data matching unit for selecting 0-th through thirty first CPU data or 0-th through thirty first VMEbus data from the local system in accordance with the control signal from the control bus, and for checking a parity during a data transmission and receiving operation. The dual port RAM matching circuit further includes a control signal matching unit for selecting either the control signal from the local system or the control signal from the VMEbus in accordance with the control signal from the control bus and for outputting the selected control signal to the control bus, and a control signal generator for receiving an address information signal and a clock signal from the local system, and an address information signal from the VMEbus, and outputting control signals to the control bus.

Growing community of inventors

Daejeon-si, South Korea

Woon-Seob So