Samsung Electronics Co., Ltd.

Woon-Kyung Lee

Dong-yean Oh

Sung-Min Hwang

Jeong-Hyuk Choi

Jai-Hyuk Song

Han-Soo Kim

Seung-jun Lee

Won-Seok Cho

Seung-Chul Lee

Eui-Do Kim

Jin-Sung Lee

Sang-Yong Park

Sun-Young Kim

Chang-Sub Lee

Jae-Joo Shim

Jong-Won Kim

Jin-taek Park

Ju-Young Lim

Sung-bu Jun

Dong-Whee Kwon

Dongyean Oh

Dong-Jun Lee

Young-Ho Lee

Ju-Hyung Kim

Han-soo Kim

Chang-Seok Kang

Seong-Soon Cho

Yun-Heub Song

Youn-Ho Lee

Hui-Chang Moon

Jung-Min Son

Seung-wan Hong

Jai Hyuk Song

Jeong-Hyouk Choi

Jong-Kwang Lim

Step shape pad structure and wiring structure in vertical type semiconductor device are include a first conductive line having a first line shape and including first pad regions at an upper surface of an edge portion, and a second conductive line having s second line shape and being spaced apart from the first conductive line and provided on the first conductive line. An end portion of the first conductive line is extended to a first position. Second pad regions are included on an upper surface of an edge portion of the second conductive line. An end portion of the second conductive line is extended to the first position. The second conductive line includes a dent portion at a facing portion to the first pad regions in a vertical direction to expose the first pad regions. The pad structure may be used in a vertical type nonvolatile memory device.

Pad structures and wiring structures in a vertical type semiconductor device

An integrated circuit includes a NAND string including a string selection transistor SST and a ground selection transistor GST disposed at either end of series-connected memory storage cells MC. Each of the memory storage cells is a memory transistor having a floating gate, and at least one of the string selection transistor SST and the ground selection transistor GST is a memory transistor having a floating gate. The threshold voltage Vth of programmable string selection transistors SST and the ground selection transistor GST is variable and user controllable and need not be established by implantation during manufacture. Each of the programmable string selection transistors SST and the ground selection transistors GST in a memory block may be used to store random data, thus increasing the memory storage capacity of the flash memory device.

NAND flash memory device and method of making same

A method of fabricating a semiconductor device includes forming a stacked structure in which 2(here, n is an integer which is 2 or more) deposited sacrificial layers and 2deposited insulating layers disposed on the 2deposited sacrificial layers respectively are alternately deposited in a third direction perpendicular to a first direction and a second direction on a substrate having an upper surface extending in the first and second directions which are perpendicular to each other. Methods include forming a recess group including 2&#x2212;1 first recesses penetrating 2through 2deposited sacrificial layers and forming a buried insulating layer group including 2&#x2212;1 buried insulating layers filling the 2&#x2212;1 first recesses respectively. A contact plug group including 2contact plugs penetrating an uppermost deposited insulating layer of the 2deposited insulating layers and the 2&#x2212;1 buried insulating layers may be formed.

Methods of fabricating semiconductor devices

A vertical type semiconductor device includes first and second word line structures that include first and second word lines. The word lines surround a plurality of pillar structures, which are provided to connect the word lines to corresponding string select lines. Connecting patterns electrically connect pairs of adjacent first and second word lines in a same plane. The device may be a nonvolatile memory device or a different type of device.

Vertical type semiconductor devices

A method of manufacturing a vertical type memory device includes stacking a first lower insulating layer, one layer of a lower sacrificial layer and a second lower insulating layer on a substrate, forming a stacking structure by stacking sacrificial layers and insulating layers, and etching an edge portion of the stacking structure to form a preliminary stepped shape pattern structure. The preliminary stepped shape pattern structure has a stepped shape edge portion. A pillar structure making contact with a surface of the substrate is formed. The preliminary stepped shape pattern structure, the lower sacrificial layer, and the first and second lower insulating layers are partially etched to form a first opening portion and a second opening portion to form a stepped shape pattern structure. The second opening portion cuts at least an edge portion of the lower sacrificial layer.

Methods of manufacturing a semiconductor device

Provided is a semiconductor device that includes first and second isolation patterns disposed on a substrate. Alternately stacked interlayer insulating patterns and a conductive patterns are disposed on a surface of the substrate between the first and second isolation patterns. A support pattern penetrates the conductive patterns and the interlayer insulating patterns and has a smaller width than the first and second isolation patterns. First and second vertical structures are disposed between the first isolation and the support pattern and penetrate the conductive patterns and the interlayer insulating patterns. A second vertical structure is disposed between the second isolation pattern and the support pattern and penetrates the conductive patterns and the interlayer insulating patterns. A distance between top and bottom surfaces of the support pattern is greater than a distance between a bottom surface of the support pattern and the surface of the substrate.

Semiconductor device with vertical structures that penetrate conductive patterns and interlayer insulating patterns

A nonvolatile memory device comprises a channel pattern, a first interlayer dielectric film and a second interlayer dielectric film spaced apart from each other and stacked over each other, a gate pattern disposed between the first interlayer dielectric film and the second interlayer dielectric film, a trap layer disposed between the gate pattern and the channel pattern and a charge spreading inhibition layer disposed between the channel pattern and the first interlayer dielectric film and between the channel pattern and the second interlayer dielectric film. The charge spreading inhibition layer may include charges inside or on its surface. The charge spreading inhibition layer includes at least one of a metal oxide film or a metal nitride film or a metal oxynitride film having a greater dielectric constant than a silicon oxide film.

Nonvolatile memory device and fabricating method thereof

Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device may include first transistors that include a first gate insulating layer having a first thickness and second transistors include a second gate insulating layer having a second thickness less than the first thickness. At least one of the transistors formed on the first or second gate insulating layers may be directly over a dummy well.

Semiconductor device comprising a dummy well

A memory device includes a substrate having a cell array region defined therein. A dummy structure is disposed on or in the substrate near a boundary of the cell array region. The memory device also includes a vertical channel region disposed on the substrate in the cell array region. The memory device further includes a plurality of vertically stacked conductive gate lines with insulating layers interposed therebetween, the conductive gate lines and interposed insulating layers disposed laterally adjacent the vertical channel region and extending across the dummy structure, at least an uppermost one of the conductive gate lines and insulating layers having a surface variation at the crossing of the dummy structure configured to serve as a reference feature. The dummy structure may include a trench, and the surface variation may include an indentation overlying the trench.

Vertical nonvolatile memory devices having reference features

Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device can include first transistors that include a first gate insulating layer having a first thickness and second transistors include a second gate insulating layer having a second thickness less than the first thickness. At least one of the transistors formed on the first or second gate insulating layers is directly over a dummy well.

Method of fabricating semiconductor device comprising a dummy well

A nonvolatile memory device and a method of forming a nonvolatile memory device are provided. The nonvolatile memory device includes an active region of a semiconductor substrate defined by a device isolation layer, a tunnel insulating structure disposed on the active region, and a charge storage structure disposed on the tunnel insulating structure. The nonvolatile memory device also includes a gate interlayer dielectric layer disposed on the charge storage structure, and a control gate electrode disposed on the gate interlayer dielectric layer. The charge storage structure includes an upper charge storage structure and a lower charge storage structure, and the upper charge storage structure has a higher impurity concentration than the lower charge storage structure.

Nonvolatile memory device and method of forming the nonvolatile memory device including giving an upper portion of an insulating layer an etching selectivity with respect to a lower portion

An flash memory device includes a block of NAND cell units, each NAND cell unit in the block includes n memory cell transistors MC controlled by a plurality of n wordlines, and is connected in series between a string selection transistor SST connected to a bitline and a ground selection transistor GST. While a programming voltage Vpgm is applied to a selected wordline WL&#x3c;i&#x3e;, a cutoff voltage Vss is applied to a nearby unselected wordline closer to the ground selection transistor GST to isolate a first local channel Chfrom a second local channel Ch. As the location i of the selected wordline WL&#x3c;i&#x3e; increases close to the SST, the second channel potential Vchtends to increase excessively, causing errors. The excessive increase of Vchis prevented by modifying the voltages applied to string select lines (SSL) and/or to the bit lines (BL), or the pass voltages Vpass applied to the unselected wordlines (WL&#x3c;i+1 through WL&#x3c;n&#x2192;), only if the selected wordline WL&#x3c;i&#x3e; location i is equal or greater than a predetermined (stored) location number x. If incremental step pulse programming (ISPP) is implemented, the applied voltages are modified only if the ISPP loop count j is equal or greater than a predetermined (stored) critical loop number y.

NAND flash memory device and method of operating same to reduce a difference between channel potentials therein

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Seongnam-si, South Korea

Woon-Kyung Lee