Samsung Electronics Co., Ltd.

Wookyung You

Jongmin Baek

Sanghoon Ahn

Sangho Rha

Naein Lee

Nae-in Lee

Jangho Lee

Byunghee Kim

Vietha Nguyen

Suhyun Bark

Deokyoung Jung

Kyeongbeom Park

Kyu-Hee Han

Jiwon Kang

Sang Hoon Ahn

Byung-Kwon Cho

Kyuhee Han

Hak-Sun Lee

YoungWoo Cho

Songyi Han

Jiwon Yun

Young-ju Park

Sangshin Jang

Inoue Naoya

Seonghun Lim

Il Gyu Kim

Woojin Lee

Donghyun Roh

Hyunbae Lee

Jinhyung Park

Doo-Sung Yun

Thomas Oszinda

Koungmin Ryu

Chin Woo Kim

KyoungWoo Lee

Suhyun Park

Sangkoo Kang

Seungyong Yoo

Yeonggil Kim

Kyoungpil Park

Juyoung Jung

Hoyun Jeon

Sungbin Park

A semiconductor device including a first conductive layer on a substrate, a second conductive layer on the first conductive layer, a contact structure between the first and second conductive layers, and a barrier structure surrounding a lower region of a side surface of the second conductive layer, wherein the contact structure includes a contact conductive layer having a first upper surface portion and a second upper surface extending from the first upper surface portion and being concave, and a gap-fill pattern fills a space between the second upper surface portion and the second conductive layer and includes a first gap-fill insulating layer including a metal element and a second gap-fill insulating layer including a silicon element, and the barrier structure includes a first etch stop layer and a barrier layer that include same materials as the first insulating material and the second insulating material, respectively, may be provided.

Semiconductor devices

A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.

Semiconductor device

A semiconductor device including a transistor on a substrate; an interlayer insulating layer on the transistor; a first metal-containing layer on the interlayer insulating layer; and a second metal-containing layer on the first metal-containing layer, wherein the second metal-containing layer includes a resistor, the resistor includes a first insulating layer on the first metal-containing layer; a resistor metal layer on the first insulating layer; and a second insulating layer on the resistor metal layer, and the resistor metal layer includes a recessed side surface.

Disclosed is a semiconductor device comprising a substrate, a first dielectric layer on the substrate, a first lower conductive line in the first dielectric layer, an etch stop layer on the first dielectric layer, a via-structure that penetrates the etch stop layer and connects to the first lower conductive line, a second dielectric layer on the etch stop layer, and an upper conductive line that penetrates the second dielectric layer and connects to the via-structure. The first dielectric layer includes a dielectric pattern at a level higher than a top surface of the first lower conductive line. The upper conductive line is in contact with a top surface of the etch stop layer. The etch stop layer has at an upper portion a rounded surface in contact with the via-structure.

A semiconductor device includes a first insulating layer disposed on a substrate, a first wiring disposed in the first insulating layer, a first insulating barrier layer disposed on the first insulating layer, an etch-stop layer disposed on the first insulating barrier layer and having an area smaller than an area of the first insulating barrier layer in a plan view, a resistive metal pattern disposed on the etch-stop layer, a second insulating barrier layer disposed on the resistive metal pattern, a second insulating layer covering the first and second insulating barrier layers, a second wiring disposed in the second insulating layer, and a first conductive via disposed between the resistive metal pattern and the second wiring to penetrate through the second insulating barrier layer and the second insulating layer and electrically connect the resistive metal pattern and the second wiring.

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device includes a contact structure connected to an active region. A first insulating layer is disposed on a barrier dielectric layer and has a first hole connected to the contact structure. A second insulating layer is disposed on the first insulating layer and has a trench connected to the first hole. The second insulating layer has an extended portion along a side wall of the first hole. A width of the first hole less the space occupied by the extended portion is defined as a second hole. A wiring structure including a conductive material is connected to the contact structure. A conductive barrier is disposed between the conductive material and the first and second insulating layers. An etch stop layer is disposed between the first and second insulating layers and between the extended portion of the second insulating layer and a side wall of the first hole.

Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.

Semiconductor devices including a capping layer

Semiconductor devices are provided. A semiconductor device includes gaps between conductive patterns. Moreover, the semiconductor device includes a permeable layer on the conductive patterns. Methods of fabricating semiconductor devices are also provided.

Semiconductor devices and methods of fabricating the same

A method of manufacturing the semiconductor device includes providing a first interlayer dielectric layer having a conductive pattern, sequentially forming a first etch stop layer, a second etch stop layer, a second interlayer dielectric layer and a mask pattern on the first interlayer dielectric layer, forming an opening in the second interlayer dielectric layer using the mask pattern as a mask, the opening exposing the second etch stop layer, and performing an etching process including simultaneously removing the mask pattern and the second etch stop layer exposed by the opening to expose the first etch stop layer.

Method of manufacturing semiconductor device using a plurality of etch stop layers

A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the first insulating layer. The interlayer insulating layer includes a first region, and a second region including an air gap. The air gap is defined between a pair of the interconnections in the second region. A top surface of the first insulating layer of the first region is lower than a top surface of at least one of the interconnections in the first region.

Planarized interlayer dielectric with air gap isolation

A semiconductor device includes a substrate, a plurality of first conductive patterns disposed on the substrate and a plurality of second conductive patterns disposed on the first conductive patterns. Respective air gaps are disposed between adjacent ones of the first conductive patterns overlying a first region of the substrate, while adjacent ones of the first conductive patterns overlying a second region of the substrate do not have air gaps disposed therebetween. The air gaps may include first air gaps, and the device may further include second air gaps disposed between adjacent ones of the second conductive patterns in the second region. Adjacent ones of the second conductive patterns overlying a second region of the substrate may not have air gaps disposed therebetween.

Semiconductor devices having staggered air gaps

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Suwon-si, South Korea

Wookyung You