Samsung Electronics Co., Ltd.

Wook-je Kim

Mun-Mo Jeong

Chang-Huhn Lee

Jae-Man Yoon

Sang-hyun Lee

Yun-Jae Lee

Embodiments of the invention provide a semiconductor device and a fabrication method for a semiconductor device that includes the processes of forming multiple gates on a silicon substrate, forming a gate spacer having a positive slope at the gate spacer edge, depositing a polysilicon layer on the silicon substrate between the gates, etching a portion of the polysilicon layer to form an opening exposing a portion of the silicon substrate, and forming an inter-insulation layer to the exposed portion of the silicon substrate to fill the opening. Using an annealing process applied to a layer in the gate spacer, the etch selectivity can be selectively controlled and consequently, the degree of slope at the gate spacer edge is predetermined.

Semiconductor device with gate spacer of positive slope and fabrication method thereof

In a semiconductor memory device with a high operating current and a method of manufacturing the same, a semiconductor substrate is formed in which a memory cell region and a peripheral circuit region including an N-channel metal oxide semiconductor (NMOS) region and a P-channel metal oxide semiconductor (PMOS) region are defined. A gate electrode with sidewall spacers is formed in each of the memory cell region and the peripheral circuit region. Source and drain regions are formed in the semiconductor substrate at sides of the gate electrode to form metal oxide semiconductor (MOS) transistors. A first etch stop layer is formed on the semiconductor substrate where the MOS transistors are formed. A second etch stop layer is selectively formed in the NMOS region of the peripheral circuit region.

Semiconductor memory device with high operating current and method of manufacturing the same

Semiconductor device with gate space of positive slope and fabrication method thereof

A method for fabricating a semiconductor device includes preparing a semiconductor substrate having a contact pad; forming a first insulating film having a storage node contact exposing the contact pad and having a stack structure of an upper interlayer insulating film, a bottom interlayer insulating film, and an etching stopper between the upper and bottom interlayer insulating layers that protrudes into the storage node contact; forming a first conductive film for a storage node on the substrate; forming a second insulating film where a portion of a surface corresponding to the storage node contact is recessed; forming an etching mask layer on the recessed portion of the second insulating film; etching the second insulating film using the etching mask layer; forming a second conductive film for a storage node on the substrate; etching the first and second conductive films to isolate nodes; and removing the etching mask layer, the second insulating film and the upper interlayer insulating film.

Growing community of inventors

Seoul, South Korea

Wook-je Kim