Samsung Electronics Co., Ltd.

Woojin Rim

Jonghoon Jung

Jung-Ho Do

Taejoong Song

Jisu Yu

Yongho Kim

Gyuhong Kim

Hoonki Kim

Yong Ho Kim

Jongsun Park

Woong Il Choi

Seong Ook Jung

Sung Hyun Park

Tae Joong Song

Hanwool Jeong

Changnam Park

A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion.

Semiconductor device including a field effect transistor

A memory device is provided. The memory device includes a cell array having memory cells; n word lines sequentially arranged and including a first word line, an n-th word line, and word lines interposed between the first word line and the n-th word line; bit lines; a first power node located adjacent to the first word line; a second power node located adjacent to the n-th word line; a first switch connected between the first power node and the cell array; a write driver located adjacent to the n-th word line and connected to the bit lines; and a switch controller configured to control the first switch to isolate the first power node from the memory cells during a write operation on memory cells connected to the first word line.

Memory array with multiple power supply nodes and switch controllers for controlling power supply nodes for reliable write operation and method of operation

A memory device includes a memory cell array including a plurality of memory cells arranged in a plurality of columns including a normal column and a redundancy column for repairing the normal column, a plurality of peripheral logic circuits including a normal peripheral logic circuit and a redundancy peripheral logic circuit for repairing the normal peripheral logic circuit, and a first path selection logic circuit configured to form first paths between the plurality of columns and the plurality of peripheral logic circuits, based on at least one defect from among a defect in at least one of the plurality of columns or a defect in at least one of the plurality of peripheral logic circuits.

Memory device including a redundancy column and a redundancy peripheral logic circuit

An integrated circuit (IC) and a mobile device are provided. The IC includes a memory cell that includes a word line, a bit line pair, and a storage cell connected to the word line and the bit line pair. The IC further includes a timing control circuit configured to generate switch signals based on an operation control signal, and a switch circuit configured to receive a first voltage, a second voltage and a third voltage having different levels, and output, to the word line, one among the first voltage, the second voltage, and the third voltage based on the switch signals.

Integrated circuit including embedded memory device for performing dual-transient word line assist using triple power source and device having the same

A memory device includes a first memory cell array including memory cells of a single-ended bitline structure, a second memory cell array including memory cells of a single-ended bitline structure, a reference voltage generator configured to output a bitline voltage of a selected one of the first and second memory cell arrays as a sensing voltage according to an array select signal and output a bitline voltage of an unselected memory cell array as a reference voltage, and a differential sense amplifier configured to amplify and output a difference between the sensing voltage and the reference voltage. Logic states of the sensing voltage and the reference voltage are complementary to each other.

Memory device of a single-ended bitline structure including reference voltage generator

A static random access memory device may include a write driver configured to float one of a first bitline and a second bitline connected to a memory cell and apply a write voltage to the other bitline in response to a logic state of a data signal; a write failure detector configured to receive a voltage of the floated bitline and output a write failure signal; and an assist voltage generator configured to generate a write assist voltage in response to the write failure signal. The write driver may additionally provide the write assist voltage to a bitline to which the write voltage is applied.

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Hwaseong-si, South Korea

Woojin Rim