Samsung Electronics Co., Ltd.

Woojin Jeong

Junhyeok Ahn

Hui-Jung Kim

A semiconductor device includes a cell active pattern including a first portion and a second portion that are spaced apart from each other; a gate structure between the first portion and the second portion of the cell active pattern; a bit-line contact on the first portion of the cell active pattern; a connection pattern on the second portion of the cell active pattern; and a cell separation pattern in contact with the bit-line contact and the connection pattern, wherein the cell separation pattern includes a first sidewall in contact with the connection pattern and a second sidewall in contact with the bit-line contact, an upper portion of the second sidewall of the cell separation pattern is in contact with the bit-line contact, and a lower portion of the second sidewall of the cell separation pattern is spaced apart from the bit-line contact.

Semiconductor device having a cell separation pattern in contact with the bit line contact

A semiconductor memory device includes an active portion defined by a device isolation pattern, the active portion including a first impurity region located at a center portion of the active portion and a second impurity region located at an end portion of the active portion, a word line provided on the active portion and extending in a first direction, a bit line provided on the word line and extending in a second direction crossing the first direction, a bit line contact provided between the bit line and the first impurity region of the active portion, a storage node pad provided on the second impurity region of the active portion, and a storage node contact provided on the storage node pad and at a side of the bit line.

Growing community of inventors

Suwon-si, South Korea

Woojin Jeong