Micron Technology Incorporated

Woohee Kim

John David Hopkins

Justin B Dorhout

Richard J Hill

David A Daycock

Qian Tao

Brett D Lowe

Christopher J Larsen

Barbara L Casey

Changhan Kim

John A Smythe

Stefan Uhlenbrock

Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels include conductive wordline material having terminal ends. Charge blocking material is along the terminal ends of the conductive wordline material and has first vertical faces. The insulative levels have terminal ends with second vertical faces. The second vertical faces are laterally offset relative to the first vertical faces. Charge-trapping material is along the first vertical faces, and extends partially along the second vertical faces. The charge-trapping material is configured as segments which are vertically spaced from one another by gaps. Charge-tunneling material extends along the segments of the charge-trapping material. Channel material extends vertically along the stack, and is spaced from the charge-trapping material by the charge-tunneling material. The channel material extends into the gaps. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies having charge-trapping material arranged in vertically-spaced segments, and methods of forming integrated assemblies

Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.

Memory arrays, and methods of forming memory arrays

An example method comprises an ALD sequence including contacting an outer substrate surface at a temperature Twith a first precursor to form a monolayer onto the outer substrate surface. Temperature of the outer substrate surface and the monolayer thereon is increased to a temperature Tthat is at least 200&#xb0; C. greater than a maximum of the temperature T. The temperature-increasing is at a temperature-increasing rate that takes no more than 10 seconds to get the outer substrate surface and the monolayer thereon at least 200&#xb0; C. above the maximum temperature T. At the temperature T, the monolayer is contacted with a second precursor that reacts with the monolayer to form a reaction product and a new outer substrate surface that each comprise a component from the monolayer and a component from the second precursor. With the monolayer not having been allowed to be at least 200&#xb0; C. above the maximum temperature Tfor more than 10 seconds, temperature of the new outer substrate surface is decreased from the temperature Tto a lower temperature TL that is at least 200&#xb0; C. lower than a minimum of the temperature T

Methods comprising an atomic layer deposition sequence

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Seoul, South Korea

Woohee Kim