International Business Machines Corporation

Samsung Electronics Co., Ltd.

Tsinghua University

Woogeun Rhee

Daniel Joseph Friedman

Dong Wook Kim

Zhihua Wang

Xueyi Yu

Jong Jin Kim

Herschel Akiba Ainspan

Mehmet Soyuer

Babak Soltanian

Dong-wook Kim

Tae-Young Oh

Fei Chen

Sergey Vladimirovich Rylov

Bo Zhou

Joon-Young Park

Joo-sun Choi

Yong Liu

Sudhir Muniswamy Gowda

Jong-Jin Kim

Byeong-Ha Park

Hyung-Ki Ahn

Sung Cheol Shin

Sang-Soo Ko

Yuanfeng Sun

Woo-Seung Choo

He Rui

Xican Chen

Shuli Geng

A receiver, an operating method of the receiver, and a beamforming radar system including the receiver are provided. A beamforming receiver may include a demodulation circuit configured to receive a signal reflected from an object via an antenna, to demodulate the received signal, and to generate a demodulated signal, and a time delay circuit configured to generate a digital signal by processing the demodulated signal based on reference clock signals, wherein the digital signal including static delay information associated with a static motion of the object, and dynamic delay information associated with a dynamic motion of the object.

Receiver, method of operating the receiver, and beamforming radar system including receiver

A transmitter and a receiver for reducing power consumption in a frequency modulation-ultra-wideband (FM-UWB) communication system are provided. The transmitter includes a detector configured to generate a pulse signal when an edge of a digital signal is detected. The transmitter further includes a first modulator configured to modulate the digital signal into a first modulation signal based on a value of the digital signal. The transmitter further includes a second modulator configured to modulate the first modulation signal into a second modulation signal based on a frequency of the first modulation signal when the pulse signal is generated.

Transmitter and receiver for reducing power consumption in FM-UWB communication system

An apparatus and method for ultra wideband (UWB) communication, using a dual band pass filter (BPF) is disclosed. The UWB communication apparatus may include a first BPF performing a first band pass filtering with respect to a UWB signal, a second BPF that has a center frequency differing from a center frequency of the first BPF, and performs a second band pass filtering with respect to the UWB signal, a first envelope detector that detects a size of a first signal filtered in the first BPF, a second envelope detector that detects a size of a second signal filtered in the second BPF, and a demodulator that demodulates a UWB signal, using the size of the first signal and the size of the second signal.

Apparatus and method for ultra wideband communication using dual band pass filter

A pulse generation apparatus includes a delay pulse generator configured to generate a plurality of delay pulses, an amplitude modulator configured to modulate amplitudes of the plurality of delay pulses, and a Gaussian pulse generator configured to generate a Gaussian pulse based on the amplitude-modulated delay pulses.

Apparatus and method for generating Gaussian pulse and ultra wideband communication apparatus for generating Gaussian pulse

An apparatus includes a phase-locked loop (PLL) circuit including a phase-frequency detector configured to output phase error signals. A phase error monitor circuit is configured to determine instantaneous peak phase error by logically combining the phase error signals and comparing pulse widths of the logically combined phase error signals to a programmable delay time at each reference clock cycle to determine instantaneous phase error change. A storage element is configured to store the instantaneous phase error change.

Method and apparatus for on-chip phase error measurement to determine jitter in phase-locked loops

A frequency divider includes a prescaler and multiple modulus dividers commonly coupled to the prescaler. The prescaler generates intermediate frequency signals having a same phase difference with respect to one another in response to an oscillation frequency signal. The prescaler operates at a first frequency. The modulus dividers respectively divide the intermediate frequency signals with respective ratio to provide a plurality of division frequency signals in response to a control signal. The modulus dividers operate at a second frequency less than the first frequency.

Frequency divider, frequency synthesizer and application circuit

A phase-locked-loop (PLL) circuit is provided. The PLL circuit includes a phase/frequency detector, a digital filter, a digital low pass filter (LPF), a digitally controlled oscillator (DCO), and a frequency divider. The digital LPF performs a low-pass-filtering on least significant bits of first digital data in a digital mode and generates filtered second digital data. The DCO performs a digital-to-analog conversion on the second digital data and most significant bits of the first digital data to generate a first signal, generates an oscillation control signal based on the first signal, and generates an output clock signal oscillating in response to the oscillation control signal.

Phase-locked-loop circuit including digitally-controlled oscillator

Example embodiments are directed to a delay locked loop (DLL) circuit based on a hybrid finite impulse response (FIR) filtering technique, and a semiconductor memory device including the DLL circuit. The DLL circuit includes a frequency divider and a self-referenced multiphase generator (SRMG) and allows a Sigma-Delta (&#x3a3;&#x394;) modulator to operate at a low frequency without generating false lock and glitch noise.

Delay locked loop using hybrid FIR filtering technique and semiconductor memory device having the same

A delay locked loop and method and electronic device including the delay locked loop are provided. In one embodiment, the delay locked loop includes a first delay locked loop and a second delay locked loop. The first delay locked loop receives a data signal and a plurality of first clock signals, generates a plurality of second clock signals based on interpolation on the plurality of first clock signals, selects and outputs one of the second clock signals from among the plurality of second clock signals based on a locking operation on the plurality of second clock signals and the data signal, and generates a plurality of phase resolution control signals. The second delay locked loop receives the data signal, the selected second clock signal, and the plurality of phase resolution control signals, generates a plurality of third clock signals having variable phase resolution based on the selected second clock signal and at least one of the plurality of phase resolution control signals, and performs a locking operation on the plurality of third clock signals and the data signal.

Delay locked loop and method and electronic device including the same

Phase interpolation techniques for voltage-controlled delay line (VCDL) implementation are provided. The techniques of the invention may employ a second-order phase interpolation topology to improve tuning range performance of the VCDL over process and temperature variation. In one aspect of the invention, the technique may use a complementary input signal to set an absolute 180-degree phase reference. As a result, the maximum tuning range of 180 degrees can be achieved regardless of internal delay variation.

Voltage-controlled delay circuit using second-order phase interpolation

An instantaneous phase error detector (IPED) and method includes a first gate configured to logically OR output phase error signals as data to a first latch, and a second gate configured to logically combine the output phase error signals to clock the first latch. A delay element delays to the data to the first latch where the output of the first latch provides instantaneous phase error change information. A second latch is coupled to the output phase error signals to output a lead/lag signal to indicate which of the output phase error signals is leading. A phase-locked loop employing the output of the IPED is also disclosed along with static phase measurement and jitter optimization features.

Automatic static phase error and jitter compensation in PLL circuits

There are provided relaxation oscillators and methods for controlling the same. A relaxation oscillator includes a load device, a switching device, a fine-tuning varactor, and a current source. The load device is configured to provide a variable oscillator output based on a variable input reference voltage. The switching device is connected in signal communication with the load device and is configured to become active and inactive based on the variable oscillator output. The fine-tuning varactor is connected in signal communication with the switching device and is configured to provide fine-tuning of the variable oscillator output when the switching device is active. The current source is connected in signal communication with the switching device and is configured to provide coarse-tuning of the variable oscillator output when the switching device is active.

Triple-input relaxation oscillator with differential controllability

A hybrid circuit includes a current-starved voltage-controlled circuit configured to adjust a first type of signal difference, and a phase-interpolated voltage controlled circuit configured to adjust a second type of signal difference. The current-starved circuit and the phase-interpolated circuit cooperate to provide improved operational performance of the hybrid circuit.

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Beijing, China

Woogeun Rhee