Teranex, Inc.

Teranex Systems, Inc.

Lockheed Martin Corporation

Geo Semiconductor Inc.

Woodrow L Meeker

Michele D Van Dyke-Lewis

Andrew P Abercrombie

David A Duncan

Ronald W Schoomaker

Carl Alan Morris

Clara Ka Wah Sung

Systems and methods for folding a single instruction multiple data (SIMD) array include a newly defined processing element group (PEG) that allows interconnection of PEGs by abutment without requiring a row or column weave pattern. The interconnected PEGs form a SIMD array that is effectively folded at its center along the North-South axis, and may also be folded along the East-West axis. The folding of the array provides for north and south boundaries to be co-located and for east and west boundaries to be co-located. The co-location allows wrap-around connections to be done with a propagation distance reduced effectively to zero.

Folded SIMD array organized in groups (PEGs) of respective array segments, control signal distribution logic, and local memory

In an image processing system, high density storage of bit-plane data is provided in a secondary or page memory as well as high bandwidth access to the data by an image processor. The page memory provides storage of data not currently being processed. The page memory may also be part of a system that provides input and output of image data to and from the image processor. The image data may be handled outside the image processor in a packed pixel form and be converted between that form and bit-line form which the page memory stores during input and output. The bit-line data may be gathered into bit-planes for use by the image processor during movement of data from the page memory to the processing logic.

Method and apparatus for high density storage and handling of bit-plane data

System and method for the management of bit plane resources are presented. Because of the scarcity of processing element (PE) memory in a SIMD architecture, it is important to ensure that it is used with optimal efficiency. The Invention discloses methods for managing PE memory at runtime such that nearly 100% utilization is achieved. The method employed allows memory to be allocated and deallocated in single bit plane increments. Runtime allocation and deallocation occurs continuously such that it is impossible to guarantee availability of contiguous blocks of PE memory. The method employed by the invention allows scattered bit planes to be used without the necessity of expending execution time to perform 'garbage collection'.

Method and apparatus for management of bit plane resources

System and method for reading and writing pixel aligned subframes from a frame buffer in a parallel processing system are disclosed. Optimal bandwidth access of the frame buffer requires that data be moved in bursts having multiple data words. Subframes are specified at X and Y locations within the image frame with a resolution of one pixel. In addition, subframes within a row may overlap each other and consecutive subframe rows may also overlap. Memory control logic of the invention provides pixel packing and unpacking and storing selected pixel data in a cache memory. Reading and writing to the frame buffer is provided in a manner that makes optimal use of the frame buffer internal architecture. Other capabilities of the memory control logic include decimation of pixel data during input, suppression of redundant frame buffer writes, and accessing image frame data in an interlaced manner.

Method and apparatus for reading and writing pixel-aligned subframes in a frame buffer

An apparatus for processing data has a Single-Instruction-Multiple-Data (SIMD) architecture, and a number of features that improve performance and programmability. The apparatus includes a rectangular array of processing elements and a controller. In one aspect, each of the processing elements includes one or more addressable storage means and other elements arranged in a pipelined architecture. The controller includes means for receiving a high level instruction, and converting each instruction into a sequence of one or more processing element microinstructions for simultaneously controlling each stage of the processing element pipeline. In doing so, the controller detects and resolves a number of resource conflicts, and automatically generates instructions for registering image operands that are skewed with respect to one another in the processing element array. In another aspect, a programmer references images via pointers to image descriptors that include the actual addresses of various bits of multi-bit data. Other features facilitate and speed up the movement of data into and out of the apparatus. &ldquo;Hit&rdquo; detection and histogram logic are also included.

Mesh connected computed

Mesh connected computer

An apparatus for processing data has a plurality of single-bit processing elements coupled together to form an m&times;n processing element array, where m is an integer number of rows and n is an integer number of columns. Each processing element has addressable storage for storing pixel data in an array format in which each addressable storage holds all of the bits associated with one pixel; and the processing element array includes a mechanism for providing direct read/write access to the addressable storage located in any addressed row of the processing element array without requiring that data be passed through other rows of the array. The apparatus also includes an addressable input/output memory for storing pixel data in a raster scan order; and pixel corner-turning logic, coupled to the input/output memory and to the processing element array, for transferring pixel data between the input/output memory and the processing element array, and for reordering bits of the pixel data being transferred so as to convert between the raster scan order and the array format.

Directly accessing local memories of array processors for improved real-time corner turning processing

Bit-serial processors quickly multiply multiple-bit operands using significantly fewer clock cycles as compared to conventional bit-serial implementations. Exemplary embodiments process groups of operand bits simultaneously to provide the significant speed increases. Advantageously, however, the exemplary embodiments utilize logic and memory architectures which are fully compatible with, and fully useful for, conventional bit-serial applications, and the embodiments thus provide fast multiple-bit multiplications while at the same time providing all of the advantages typically associated with conventional bit-serial processors.

Methods and apparatus for performing fast multiplication operations in

Methods and apparatus for quickly dividing multiple-bit operands using bit-serial processors include strategies for eliminating the number of steps required to execute conventional division operations. According to an exemplary embodiment, a conditional subtraction step, based on a quotient bit computed during a given pass, is combined with a compare step which is used to compute a next quotient bit and which, according to conventional techniques, is ordinarily computed during a subsequent pass. Additionally, exemplary embodiments provide a zero/non-zero mask for denominator bits which extend beyond a current most significant remainder bit during a given pass. As a result, not all denominator bits need be considered during every pass. Advantageously, the methods and apparatus of the invention can provide approximately a 3 to 1 speed improvement as compared to conventional techniques.

Methods and apparatus for performing fast division operations in

A parallel processor has a controller for generating control signals, and a plurality of identical processing cells, each of which is connected to at least one neighboring cell and responsive to the controller for processing data in accordance with the control signals. Each processing cell includes a memory, a first register, a second register, and an arithmetic logic unit (ALU). An input of the first register is coupled to a memory output. The output of the first register is coupled to a second register located in a neighboring cell. An input of the second register is coupled to receive an output from a first register located in a neighboring cell. The output of the second register is coupled to an input of the ALU. In another feature, mask logic is interposed between A and B operand sources, and two inputs of the ALU. The mask logic also inputs a mask source, and in response to control signals, can output the A operand logically OR'ed with the mask, and can output the B operand logically AND'ed with the mask. In another feature, each cell includes a multiplexor coupled to a neighboring cell for selectively transmitting cell data to the neighbor, or for effectively bypassing the cell during data shift operations by transmitting data that is received from a neighboring cell to a neighboring cell. Other enhancements to a cell architecture are also disclosed.

Parallel data processor

An apparatus for processing data has a Single-Instruction-Multiple-Data (SIMD) architecture, and a number of features that improve performance and programmability. The apparatus includes a rectangular array of processing elements and a controller. The apparatus offers a number of techniques for shifting image data within the array. A first technique, the ROLL option, simultaneously shifts image planes in opposite directions within the array. A second technique, the gated shift option, makes a normal shift of an image plane to neighboring PEs conditional, for each PE, upon a value stored in a mask register of each PE. A third technique, the carry propagate option, combines the computations from multiple PEs in order to complete an n-bit operation in fewer than n clocks by forming 'supercells' within the array. The apparatus also includes a multi-bit X Pattern register and a multi-bit Y Pattern register. These registers have bit values corresponding to respective columns (for the X Pattern register) and rows (for the Y Pattern register) of the array. Patterns can be propagated from these registers into corresponding rows and columns. Further these registers can be used to receive values representing the logical OR of signals generated by individual PEs within respective rows and columns. Further, a number of global data registers are used to store information which can be broadcast back into the processing array.

Pattern generation and shift plane operations for a mesh connected

A format for representing floating point numbers reduces the overhead typically associated with parsing floating point numbers and thereby provides for significantly improved processing speeds, particularly for bit-serial processors. According to an exemplary single-precision embodiment, numbers are represented using a 36-bit data format. Extra bits in the representation according to the invention allow certain conditions, such as overflow/underflow and the zero-ness of a number, to be detected and asserted quickly. Other conditions, such as denormalization are subsumed into normal processing through the extension of an exponent range in the representation.

Growing community of inventors

Orlando, FL, United States of America

Woodrow L Meeker