Hynix Semiconductor Inc.

Skhynix Inc.

Woo Yung Jung

Guee Hwang Sim

Jong Hoon Kim

Sang Min Kim

Tae Kyung Kim

Eun Soo Kim

Yong Hyun Lim

Choi Dong Kim

Yong Chul Shin

Jae Hyun Park

Jung A Yoo

Seok Jae Shin

An image sensing device includes an upper substrate configured to include a pixel region and a first peripheral region located outside the pixel region, a lower substrate configured to include a logic region and a second peripheral region located outside the logic region, the logic region configured to generate an image based on the electrical signals from the unit pixels, light reception elements disposed over the upper substrate and configured to transmit the incident light to the pixel region, an insulation layer disposed between the upper substrate and the lower substrate, a light reception alignment mark disposed in the first peripheral region and configured to assist positioning of the light reception elements, and an alignment pattern disposed between the first peripheral region and the second peripheral region and in the insulation layer. The alignment pattern is configured to absorb light used to measure the light reception alignment mark.

Image sensing device including light reception alignment marks

An image sensing device capable of minimizing reflection of light incident upon a metal layer is disclosed. The image sensing device includes a semiconductor substrate in which at least one groove is formed, a reflection prevention layer formed over the semiconductor substrate in a manner that the at least one groove is buried by the reflection prevention layer, and a metal layer formed over the reflection prevention layer, and provided with at least one through-hole corresponding to the at least one groove.

Image sensing device

An image sensing device for minimizing light reflected from a light shielding layer is disclosed. The image sensing device includes a semiconductor layer formed to include an active pixel region and an optical black pixel region, a light shielding layer located at the optical black pixel region formed over the semiconductor layer, a first color filter layer located at the active pixel region formed over the semiconductor layer, and a second color filter layer located over the light shielding layer. Each of the first and second color filter layers includes at least one first color filter, at least one second color filter, and at least one third color filter. In the first color filter layer, the first color filter, the second color filter, and the third color filter are arranged in the same layer. In the second color filter layer, the first color filter and the second color filter are arranged in the same layer whereas the third color filter is formed in another layer different from the layer of the first and second color filters.

A semiconductor device including a first stacked structure including first conductive layers and first insulating layers stacked alternately with each other, first semiconductor patterns arranged in a first direction, wherein each of the first semiconductor patterns passes through the first stacked structure in a stacking direction, a second stacked structure including second conductive layers and second insulating layers stacked alternately with each other, second semiconductor patterns arranged in the first direction and adjacent to the first semiconductor patterns in a second direction crossing the first direction, wherein each of the second semiconductor patterns passes through the second stacked structure in the stacking direction, a third stacked structure including air gaps and third insulating layers stacked alternately with each other and located between the first and second structures, and at least one blocking pattern passing through the third stacked structure in the stacking direction and contacting the first and second structures.

Semiconductor device

A method of forming patterns is provided. The method includes forming a resist layer on a substrate, forming a lattice-shaped extrusion barrier region in the resist layer to define pattern transfer regions corresponding to a plurality of separate windows, and positioning a template on the resist layer so that a patterned surface of the template faces the resist layer. The patterned surface provides a plurality of transfer patterns. The template is pressed to perform an imprint step for embedding the transfer patterns of the template into the pattern transfer regions of the resist layer.

Methods of forming patterns using nanoimprint lithography

A method for forming patterns is provided. The method includes forming a resist layer on a substrate, imprinting a convex pattern and a concave pattern on the resist layer using a template, forming a silicon diffusion layer containing silicon containing diffusion species in an upper portion of the convex pattern, and selectively removing a recessed portion of the resist layer under the concave pattern using the silicon diffusion layer as an etch mask.

Methods of forming patterns using imprint process

A semiconductor device includes a stacked structure including conductive layers and insulating layers stacked alternately with each other, first semiconductor patterns passing through the stacked structure and arranged in a first direction, second semiconductor patterns passing through the stacked structure and arranged in the first direction, wherein the second semiconductor patterns are adjacent to the first semiconductor patterns in a second direction crossing the first direction, air gaps located between the first semiconductor patterns and the second semiconductor patterns and extending in the first direction, and at least one blocking pattern passing through the stacked structure and filling portions of the air gaps.

Semiconductor device and method of manufacturing the same

An alignment key of a semiconductor device includes: a material layer formed at a scribe region of a semiconductor substrate, a first dummy hole and a second dummy hole passing through the material layers, a first channel insulation layer formed inside the first dummy hole, a second channel insulation layer formed inside the second dummy hole, a first capping layer formed on a side wall of an upper portion of the first dummy hole and an upper portion of the first channel insulation layer, and a second capping layer formed on a side wall of an upper portion of the second dummy hole and an upper portion of the channel insulation layer, having a height of a lower surface portion greater than that of a lower surface portion of the first capping layer.

Alignment key of semiconductor device and method of fabricating the same

A method of manufacturing a semiconductor device includes forming stepped stack structures each including conductive patterns stacked in a shape of steps while exposing respective ends thereof and surrounding channel layers, the stepped stack structures being separated from one another by slits, forming first and second contact plugs connected to the ends of the conductive patterns to extend along an extending direction of the channel layers, and simultaneously forming, using a spacer patterning technology (SPT), bit lines connected to one or more of the channel layers and extending along a first direction, first connecting lines extending along a second direction intersecting the first direction, and contact pads extending from the first connecting lines to be connected to the first contact plugs.

A semiconductor device includes contact structures and conductive wires formed over the contact structures and coupled to the respective contact structures. Part of each of the conductive wires crosses the contact structure.

Semiconductor device and forming method of the same

The present invention relates to a method of forming micro patterns of a semiconductor device. In the method according to an aspect of the present invention, first etch mask patterns having a second pitch, which is twice larger than a first pitch of target patterns, are formed in a column direction over a semiconductor substrate. An auxiliary film is formed over the semiconductor substrate including a surface of the first etch mask patterns. An etch mask film is formed over the semiconductor substrate including the auxiliary film. An etch process is performed in order to form second etch mask patterns having the second pitch in such a manner that the etch mask film, the auxiliary film, and the first etch mask patterns are isolated from one another in a row direction and the etch mask film remains between the first etch mask patterns. The auxiliary film between the first and second etch mask patterns is removed.

Method of forming micro pattern of semiconductor device

In a method of forming patterns of a semiconductor device, a semiconductor substrate defining photoresist patterns formed over a target etch layer is provided. An auxiliary layer is formed over the semiconductor substrate and the photoresist patterns. The auxiliary layer formed on a surface of the photoresist patterns is denatured into first auxiliary patterns. A photoresist film is formed over the semiconductor substrate, the first auxiliary patterns, and the auxiliary layer. The auxiliary layer formed below the photoresist film is denatured into a second auxiliary pattern. Here, the auxiliary layer remains only between the photoresist patterns. Etch mask patterns, including the photoresist patterns and the auxiliary layer, are formed by removing the photoresist film and the first and second auxiliary patterns.

Method of forming patterns of semiconductor device

In a method of forming a hard mask pattern in a semiconductor device, only processes for forming patterns having a row directional line shape and a column directional line shape on a plane are performed so that the hard mask patterns can be formed to define densely disposed active regions. A pitch of the hard mask patterns is less than a resolution limit of an exposure apparatus.

Method of forming a hard mask pattern in a semiconductor device

A pattern for a gate line is formed using a first photoresist pattern and a first BARC layer. A pad and patterns for a select line, which has a width that is larger than that of the gate line, are formed using a second photoresist pattern and a second BARC layer. The gate line, the pad and the select line can be formed at a same time.

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Seoul, South Korea

Woo Yung Jung