Skhynix Inc.

Woo Tae Lee

Beom Seok Lee

Hwan Jun Zang

Sang Hyun Ban

Tae Yong Lee

Hye Jung Choi

Jong Ho Lee

Young Ho Lee

Jun Ku Ahn

Sung Lae Cho

Uk Hwang

Gwang Sun Jung

Ye Cheon Cho

A semiconductor device and a method for fabricating the same may be provided. The semiconductor device may include: a first semiconductor structure including a substrate, a plurality of first word lines, a plurality of first bit lines, and a plurality of first memory cells respectively disposed in intersection regions between the first word lines and the first bit lines; and a second semiconductor structure including a plurality of second bit lines disposed over the first bit lines and respectively contacting the first bit lines, a plurality of second word lines, and a plurality of second memory cells respectively disposed in intersection regions between the second word lines and the second bit lines, wherein a first bit line and a corresponding second bit line form a metal-to-metal bonding.

Semiconductor device and method of fabricating the same

A chalcogenide material may include germanium (Ge), arsenic (As), selenium (Se) and from 0.5 to 10 at % of at least one group 13 element. A variable resistance memory device may include a first electrode, a second electrode, and a chalcogenide film interposed between the first electrode and the second electrode and including from 0.5 to 10 at % of at least one group 13 element. In addition, an electronic device may include a semiconductor memory. The semiconductor memory may include a column line, a row line intersecting the column line, and a memory cell positioned between the column line and the row line, wherein the memory cell comprises a chalcogenide film including germanium (Ge), arsenic (As), selenium (Se), and from 0.5 to 10 at % of at least one group 13 element.

Chalcogenide material, variable resistance memory device and electronic device

An electronic device includes a semiconductor memory. The semiconductor memory includes word lines, bit lines intersecting the word lines, and memory cells coupled to and disposed between the word lines and the bit lines, each of the memory cells including a variable resistance layer in an amorphous state regardless of a value of data stored in the memory cells. In a reset operation, a memory cell is programmed to a high-resistance amorphous state by applying, to the memory cell, a sub-threshold voltage that is lower than a lowest threshold voltage among threshold voltages of the memory cells.

Electronic device and method of operating memory cell in the electronic device

An electronic device includes a semiconductor memory. The semiconductor memory includes a word line, a bit line, and a memory cell coupled to and disposed between the word line and the bit line, the memory cell including a variable resistance layer that remains in an amorphous state regardless of a value of data stored in the memory cell. In a reset operation, the memory cell is programmed to a high-resistance amorphous state by applying, to the memory cell, a sub-threshold voltage that is greater than 0.7 time of a threshold voltage of the memory cell and is smaller than 0.95 time of the threshold voltage.

A method of manufacturing an electronic device including a semiconductor memory may include forming a first active layer, forming a first electrode material over the first active layer, performing a heat treatment process on the first electrode material and the first active layer, and forming a second electrode material over the heat-treated first electrode material.

Growing community of inventors

Icheon, South Korea

Woo Tae Lee