Samsung Electronics Co., Ltd.

Woo-Sung Yang

Kyoung-Hoon Kim

Hyun-Min Lee

Kwan-Yong Kim

Jee-hoon Hwang

Sung-Min Hwang

Ji-Young Kim

Joon-Sung Lim

Ji-Won Kim

A vertical semiconductor device including a plurality of vertical memory cells on an upper surface of a first substrate, an adhesive layer on a lower surface of the first substrate that is opposite to the upper surface of the first substrate, a second substrate having first peripheral circuits thereon, a lower insulating interlayer on the second substrate, and a plurality of wiring structures electrically connecting the vertical memory cells and the first peripheral circuits. A lower surface of the adhesive layer and an upper surface of the lower insulating interlayer may be in contact with each other.

Vertical semiconductor devices including vertical memory cells and peripheral circuits under the vertical memory cells

Semiconductor devices are provided. A semiconductor device includes first and second stacks of electrodes. Moreover, the semiconductor device includes first and second connection lines that connect the first and second stacks of electrodes. In some embodiments, the first connection lines have a first length and the second connection lines have a second length that is longer than the first length of the first connection lines. In some embodiments, the first connection lines connect inner portions of the first stack of electrodes to inner portions of the second stack of electrodes. In some embodiments, the second connection lines connect outer portions of the first stack of electrodes to outer portions of the second stack of electrodes.

Semiconductor devices including stacked electrodes

A semiconductor device includes a plurality of line patterns formed apart from one another on a substrate, the plurality of line patterns having a first width and extending parallel to one another in a first direction. A first line pattern of the plurality of line patterns may include a wider portion having a second width in a second direction perpendicular to the first direction that is greater than the first width. One or more second line patterns may be located adjacent to the first line pattern and include a conformal portion conformally formed about the wider portion of the first line pattern. One or more third line patterns may be located adjacent to the second line pattern and include an end portion near the conformal portion of the one or more second line pattern.

Semiconductor device and method of manufacturing a semiconductor device

Growing community of inventors

Gwangmyeong-si, South Korea

Woo-Sung Yang