Samsung Electronics Co., Ltd.

Woo-Sung Lee

Jung-Hwan Kim

Sang-Hoon Lee

Ji-Hoon Choi

Jung-Geun Jee

Seok-Hoon Kim

Su-Jin Shin

Tae-Ouk Kwon

Sung-Gil Kim

Chan-Ho Jung

Chan-Hyoung Kim

Ki-Hyun Hwang

Jae-Ho Choi

Jae-hyoung Choi

Nam-Kyu Kim

Hun-Hyeoung Leam

Tae-Han Kim

Jae-Jong Han

Young-sub You

Jung-hee Chung

Bong-hyun Kim

Hun-hyeong Lim

Man-Sug Kang

Seung-Mok Shin

Sang-Jin Park

Kyong-Won An

Eun-Kuk Chung

Keum-Joo Lee

Sung-Ho Heo

Myang-Sik Han

Hun-Hyeoung Lim

Hong-Bum Park

A vertical memory device may include a channel connecting pattern on a substrate, gate electrodes spaced apart from each other in a first direction on the channel connecting pattern, and a channel extending in the first direction through the gate electrodes and the channel connecting pattern. Each of the electrodes may extend in a second direction substantially parallel to an upper surface of the substrate, and the first direction may be substantially perpendicular to the upper surface of the substrate. An end portion of the channel connecting pattern in a third direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the second direction may have an upper surface higher than an upper surface of other portions of the channel connecting pattern except for a portion thereof adjacent the channel.

Vertical memory devices

Apparatuses are provided for connecting electronic devices. An apparatus includes short-range communication circuitry; a communication software module; and a processor adapted to connect with a wireless access point (AP); broadcast, using the short-range communication circuitry, a request message to perform a service associated with file sharing or conferencing, the request message including a unique identifier or a unique name related to the service; receive, via the wireless AP, a response message from at least one external device connected with the wireless AP; establish a communicative connection with the at least one external device via the wireless AP; and perform, using the communication software module, an operation for the service with the at least one external device.

Method for connection between electronic devices and electronic device thereof

Methods and apparatuses are provided for connecting electronic devices. A first electronic device broadcasts a message including at least one of related service information and connectivity information necessary for accessing a wireless access point (AP) accessed by the first electronic device, by using short-range communication. The first electronic device receives a connection request from at least one second electronic device via the wireless AP.

A nonvolatile memory device includes an insulating pattern extending in a first direction, a conductive pattern on the insulating pattern, and an electrode structure extending in the first direction. The electrode structure is adjacent the insulating pattern and conductive pattern, and includes an alternating pattern of gate electrodes and interlayer insulating films. A protection film adjacent a side surface of the electrode structure has a shorter length in the first direction than a length of the electrode structure.

Nonvolatile memory device and method for fabricating the same

A non-volatile memory device includes a field region that defines an active region in a semiconductor substrate, a floating gate pattern on the active region, a dielectric layer on the floating gate pattern and a control gate on the dielectric layer. The control gate includes a first conductive pattern that has a first composition that crystallizes in a first temperature range, and a second conductive pattern that has a second composition that is different from the first composition and that crystallizes in a second temperature range that is lower than the first temperature range, the first conductive pattern being between the dielectric layer and the second conductive pattern.

Non-volatile memory devices and methods of manufacturing the same

A method of forming a gate structure includes forming a tunnel insulation layer pattern on a substrate, forming a floating gate on the tunnel insulation layer pattern, forming a dielectric layer pattern on the floating gate, the dielectric layer pattern including a first oxide layer pattern, a nitride layer pattern on the first oxide layer pattern, and a second oxide layer pattern on the nitride layer pattern, the second oxide layer pattern being formed by performing an anisotropic plasma oxidation process on the nitride layer, such that a first portion of the second oxide layer pattern on a top surface of the floating gate has a larger thickness than a second portion of the second oxide layer pattern on a sidewall of the floating gate, and forming a control gate on the second oxide layer.

Gate structures

Example embodiments relate to a method of manufacturing a capacitor and a method of manufacturing a semiconductor device using the same. Other example embodiments relate to a method of manufacturing a capacitor having improved characteristics and a method of manufacturing a semiconductor device using the same. In a method of manufacturing a capacitor having improved characteristics, an insulation layer, including a pad therein, may be formed on a substrate. An etch stop layer may be formed on the insulation layer. A mold layer may be formed on the etch stop layer. The mold layer may be partially etched by a first etching process to form a first contact hole exposing the etch stop layer. The mold layer may be partially etched by a second etching process to form a second contact hole. The exposed etch stop layer may be etched by a third etching process to form a third contact hole exposing the pad. A native oxide layer on the exposed pad may be removed by a fourth etching process to form a capacitor contact hole. A conductive layer may be formed in the capacitor contact hole to form a capacitor.

Method of manufacturing a capacitor and method of manufacturing a semiconductor device using the same

Example embodiments relate to a capacitor, a method of forming the same, a semiconductor device having the capacitor and a method of manufacturing the same. Other example embodiments are directed to a capacitor having an upper electrode structure including a first upper electrode and a second upper electrode, a method of forming the same, a semiconductor device having the capacitor and a method of manufacturing the same. In a method of forming a capacitor, a lower electrode may be formed on a substrate, and then a dielectric layer may be formed on the lower electrode. An upper electrode structure may be formed on the dielectric layer. The upper electrode structure may include a first upper electrode and a second upper electrode. The second upper electrode may include at least two of a silicon layer, a first silicon germanium layer and a second silicon germanium layer doped with p-type impurities. The upper electrode structure may be formed without generating voids between the dielectric layer and the upper electrode structure. The capacitor and the semiconductor device having the upper electrode structure may have improved electrical characteristics.

Capacitor, method of forming the same, semiconductor device having the capacitor and method of manufacturing the same

In accordance with a method of trench isolation, a first oxide layer is formed on a semiconductor substrate. A first conductive layer and a nitride layer are successively formed on the first oxide layer. The nitride layer, the first conductive layer and the first oxide layer are etched to form a nitride layer pattern, a first conductive layer pattern and an oxide layer pattern. A portion of the substrate adjacent to the first conductive layer pattern is etched to form a trench in the substrate. The trench is cured under dinitrogen monoxide (NO) or nitrogen monoxide(NO) atmosphere. A second oxide layer is formed in the trench through an in-situ process.

Method of trench isolation and method for manufacturing a non-volatile memory device using the same

A first gate oxide layer pattern having a first thickness is formed in a first region of a substrate and a second gate oxide layer having a second thickness is formed in a second region of a substrate. A surface of the second gate oxide layer is selectively nitrified to form an oxynitride layer, thereby reducing a depletion effect of a poly gate and a fluctuation of threshold voltage.

Method of forming a gate oxide layer in a semiconductor device and method of forming a gate electrode having the same

A method of forming a gate structure of a semiconductor device includes forming a gate insulation film and a polysilicon film on a semiconductor substrate where an active region and a field region are defined, followed by forming a buffer layer on the polysilicon film to minimize damage to the polysilicon film during a subsequent ion implantation process. The polysilicon film is made electrically conductive by the implanting of impurities into the polysilicon film. Gate patterns are then formed by etching the conductive polysilicon film and the gate insulation film. Defects, such as active pitting, associated with dual electrodes are effectively prevented because the polysilicon film is protected during the ion implanting process.

Method of forming gate electrode structure of a semiconductor device

A semiconductor device including a stacked gate having stacked gate sidewalls and an oxide/nitride/oxide (ONO) interlayer dielectric is manufactured by pre-annealing the stacked gate in a first atmosphere that includes nitrogen. At least a portion of the stacked gate sidewalls of the stacked gate that has been pre-annealed is oxidized. Post-annealing is then performed on the stacked gate including the stacked gate sidewalls that have been oxidized, in a second atmosphere that includes nitrogen.

Methods for manufacturing stacked gates including oxide/nitride/oxide (ONO) interlayer dielectrics using pre-annealing and/or post-annealing in nitrogen

Growing community of inventors

Yongin-si, South Korea

Woo-Sung Lee