Samsung Electronics Co., Ltd.

University-Industry Cooperation Group of Kyung Hee University

Lg Electronics Inc.

Lg-nortel Co., Ltd.

Soosan Special Purpose Vehicle Co., Ltd.

Woo-Sik Kim

Choul-Su Kim

Taekyung Yu

Byung-Woo Woo

Ji-Hye Yi

Jong-Ho Park

Chang-Won Choi

Shin-woo Nam

Bum-su Kim

Masaharu Sukue

Kwang-Eun Ahn

Ji-hye Yi

Dae-hyuk Chung

Ji-hwan Choi

Yeo-cheol Yoon

Jonghee Han

Nae-in Lee

Seung-Hwan Lee

Young-Woo Park

Jun Hyuk Seo

Sung Pil Yoon

Dae-Jin Kwon

Jinsoo Kim

Sang Hyuk Im

Kwan Sik Kim

Jong-Heui Song

Masaharu Tsukue

Hyun-min Choi

Hwan-Young Jae

Wang-Rae Kim

Aasim Shahzad

Minyoung Yi

Su Ha

Sung-Beom Sim

Han-Seul Choi

Sang-Beom Sim

Hak-Won Kim

Chwll-Hwa Park

Maeda Shigenobu

Dae-Seung Kim

Sung-Rey Wi

Byung-Ro Song

Zengmin Tang

Wang-Xiao Quan

Jin-Sub Moon

Zaohui Wu

Provided is a method for preparing molybdenum oxide nanoparticles, including (a) preparing a precursor solution by dissolving a molybdenum salt in a first polar solvent, (b) generating an aerosol by applying ultrasonic waves to the precursor solution, and spraying the aerosol to a pre-heated reactor using a carrier gas, (c) obtaining molybdenum oxide micron-sized particles by pyrolyzing the aerosol, and (d) obtaining molybdenum oxide nanoparticles by dispersing the molybdenum oxide micron-sized particles in a second polar solvent and performing a solvothermal reduction reaction.

Method for preparing molybdenum oxide nanoparticles

Provided is a preparation method of copper nanostructures, characterized in that a copper precursor including halide is reacted with polyethyleneimine (PEI) and a reducing agent in an aqueous solution. According to this method, the copper nanostructures may be easily prepared in a sphere, wire, or plate form, and high-quality copper nanostructures may be produced with a high production yield of 90% or more. This method is also appropriate for large-scale production.

Preparation method of copper nano-structures

The present invention relates to a method for preparing metal nanoparticles, specifically, by reducing a precursor of metal or metal oxide in an aqueous solution, wherein polyethylenimine and an additional reducing agent are used, thereby obtaining metal nanoparticles having superior properties in improved yield. According to the preparation method of the present invention, metal nanoparticles can be prepared at a higher concentration of metal precursor. Further, a short reaction time and the use of a solvent that is easy to handle, such as water, allow mass production of metal nanoparticles with high efficiency. Moreover, nanoparticles having a superior property can be prepared without a high-temperature treatment over 100&#xb0; C. Accordingly, the method for preparing metal nanoparticles of the present invention may innovatively simplify the preparation processes, and may also improve the working environment. Thus, it is useful for mass production of metal nanoparticles.

Method for preparing metal nanoparticles using a multi-functional polymer and a reducing agent

The present invention relates to a method for conducting deracemization using Taylor flow and a device for conducting the same. With respect to the deracemization of a racemate, it may be efficiently conducted with improved rapidity when a racemate-containing fluid is placed under Taylor flow.

Method for conducting deracemization using Taylor flow and a device therefor

A semiconductor device includes a fuse transistor for fuse programming and a fuse block connected to the fuse transistor, wherein the fuse block comprises a fuse line and a heat spreading structure connected to the fuse line. The electrical fuse employs the heat spreading structure connected to the fuse line to prevent a rupture of the electrical fuse such that heat, which is generated in the fuse line during a blowing of the fuse line, is spread throughout the heat spreading structure. Thus, a sensing margin of the electrical fuse can be secured and a deterioration of devices adjacent to the electrical fuse by heat generated in the electrical fuse can be prevented.

Electronic fuse having heat spreading structure

A signal transmission apparatus comprises a plurality of look-up tables (LUTs) corresponding to operation areas of a nonlinear transmission device, an operational characteristic calculator, a LUT selector, and a predistorter. The LUTs are adapted to store gain values of input signal magnitudes. The LUT selector selects a LUT corresponding to a calculated operational characteristic. The selected LUT generates a gain value output signal. The predistorter generates a predistorted signal from the gain value output signal and an input signal. The predistorted signal is input to a nonlinear transmission device.

Signal transmission apparatus and method

An apparatus and a method for compensating an error of an AQM measuring and compensating the error using returned I/Q digital signals calculate the error compensating signal is disclosed. The process includes detecting a DC offset signal by averaging sampling values of returned I/Q digital signals; detecting a gain compensating signal using a maximum value in a period of the I/Q digital signals of which the DC offset is compensated; and detecting a phase compensating value of the I/Q digital signals on the basis of sum of absolute values for differences between the gain compensated I-digital signals and Q-digital signals, and remove phase error, gain error and DC offset of the inputted digital signal sequentially to compensate the AQM error.

Apparatus and method for compensating error for analog quadrature modulator (AQM)

A transmission power detecting apparatus of a CDMA system is disclosed by which since the power detection of the RF CDMA signal is digitally performed and no RF device (an RSSI detector) which is sensitive to a temperature change is used, a power of the RF CDMA signal can be more accurately detected. In addition, since an IF analog CDMA signal to be measure is sampled and then an average power of the sampled digital IF CDMA signal is obtained, accuracy in power detection and transmission power adjustment can be accomplished. Moreover, since the power of the baseband digital CDMA signal containing a traffic is detected to provide a reference value for adjusting the power of the RF CDMA signal, an error generated in determining a power of the RF CDMA signal as in the conventional art can be reduced.

Apparatus for detecting and adjusting transmission power of CDMA system

The present invention discloses a semiconductor memory device having a multiple tunnel junction pattern and a method of forming the same. The semiconductor memory device includes a unit cell composed of planar transistor and vertical transistors. The planar transistor includes first and second conductive regions formed at predetermined regions of a semiconductor substrate and a storage node stacked on a channel region therebetween. The vertical transistor includes a storage node, a multiple tunnel junction pattern stacked thereon, a data line stacked thereon, and a word line for covering both sidewalls of the storage node and the multiple tunnel junction pattern. Width of the multiple tunnel junction pattern is narrower than the storage node and data lines. Semiconductor layers and tunnel oxide layers are alternately and repeatedly stacked and anisotropically etched to form the multiple tunnel junction pattern of narrow width while forming the data line and the storage node.

Semiconductor memory device having a multiple tunnel junction pattern and method of fabricating the same

A base station transmitter having a digital predistorter and predistortion method is disclosed. The predistortion is accomplished by delaying a digital input signal, predistorted by a predistortion unit, for a predetermined time. A coefficient of a non-linear characteristic model of a power amplifier is generated using a digital output signal, converted from an amplified output signal of the power amplifier, and the delayed digital input signal. A reference signal is randomly generated to produce a predistortion model having a characteristic opposite to the non-linear characteristic of the power amplifier. A predistortion error function is extracted by subtracting the reference signal and the non-linear characteristic model of the power amplifier, after the produced coefficient is applied to the model. A coefficient of the predistortion unit is controlled adaptively using the predistortion error function. Thus, the present invention increases a precision of predistortion, the linearity of the base station transmitter, and the performance of a base transceiver system.

Base station transmitter having digital predistorter and predistortion method thereof

A semiconductor device having a chamfered silicide layer and a manufacturing method of the same. The semiconductor device includes: a first insulation layer overlying a semiconductor substrate; gate structures including first conductive layer patterns formed on the first insulation layer, and second conductive layer patterns which are formed on the first conductive layer patterns, wherein the lower sides of the second conductive layer patterns are substantially perpendicular to the major surface of the semiconductor substrate and the upper sides of the second conductive layer patterns are chamfered; and a second insulation layer formed with a first width W on the second conductive layer patterns, wherein the sidewalls of the second insulation layer overhang the upper edges of the second conductive layer patterns. In the semiconductor device manufacture, in forming undercut regions which define the chamfered upper edges of the metal silicide layer patterns, isotropic dry etching is carried out, wherein the isotropic dry etching can be performed simultaneously with ashing of photoresist patterns, or immediately after the ashing process in the same chamber. In either case, after the ashing of the photoresist patterns, an isotropic wet etching can be carried out immediately after performing an existing stripping process, so as to form the undercut regions.

Methods of manufacturing semiconductor devices having chamfered silicide layers therein

A method of forming a CMOS type semiconductor device having dual gate includes forming a first gate insulation layer and a first metal-containing layer sequentially on a surface of a substrate in first and second impurity type transistor regions, removing the first metal-containing layer and the first gate insulation layer in the second impurity type transistor region, forming a second gate insulation layer and a second metal-containing layer in the second impurity type transistor region, and forming first and second electrodes in the first and second impurity type transistor regions, respectively, by patterning the first and second metal-containing layers. When first and second impurities in the transistor regions are p-type and n-type impurities, respectively, a fermi level of the first metal-containing layer has an energy level similar to the valence band of the silicon layer in the first impurity type transistor region heavily doped by a p-type impurity, and a fermi level of the second metal-containing layer has an energy level similar to the conduction band of the silicon layer in the second impurity type transistor region heavily doped by an n-type impurity.

Method of forming a CMOS type semiconductor device having dual gates

A semiconductor memory device and fabricating method thereof, wherein the semiconductor memory device includes first and second conductive regions formed in parallel at predetermined regions of a semiconductor substrate, a storage node and a multiple tunnel junction layer pattern sequentially stacked on a channel region between the first and second conductive regions, a data line stacked on the multiple tunnel junction layer pattern, and a wordline covering both sidewalls of the storage node and of the multiple tunnel junction layer pattern, wherein both sidewalls of the storage node have undercut regions for increasing the overlapping area of the storage node and a wordline. The storage node is formed by alternately and repeatedly stacking first and second conductive layers having different etch rates, successively patterning the conductive layers to form a storage node pattern, and selectively and isotropically etching the first or second conductive layer of the storage node pattern.

Semiconductor memory device having a multiple tunnel junction layer pattern and method of fabricating the same

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Seoul, South Korea

Woo-Sik Kim