Samsung Electronics Co., Ltd.

Woo-seop Kim

Ki-sung Kim

Soo-Jin Paek

Hyun-Soo Kim

Hoe-Ju Chung

Sang-Seok Kang

Kyu-Hyoun Kim

Jae-Wook Lee

Byung-Se So

Byung-se So

Sung-bum Cho

Gyung-Su Byun

Hwan-wook Park

Jin-ho So

Hyun-Chul Kang

Jun-young Park

Dal-jo Lee

Jung-kuk Lee

Sung-Je Hong

A memory module includes a first rank, a second rank and a test control unit. The first rank includes a plurality of semiconductor memory devices configured to operate in response to a first chip selection signal. The second rank includes a plurality of semiconductor memory devices configured to operate in response to a second chip selection signal. The test control unit is configured to simultaneously enable the first and second chip selection signals to test the first and second ranks in a test mode.

Memory module and a memory test system for testing the same

A semiconductor package having a structure in which heat produced in the interior of the package is effectively spread to the outside of the package is provided. The semiconductor package includes one or more semiconductor chips, one or more substrates (PCBs) having the semiconductor chips respectively attached thereto, a plurality of conductive balls such as a plurality of solder balls to provide voltages and signals to the one or more semiconductor chips, and a heat sink positioned to spread heat produced in the interior of the package to the outside and directly connected to at least one of the plurality of solder balls.

Semiconductor package having improved heat spreading performance

A power-up/power-down detecting circuit may include a power detecting circuit, a selecting circuit, and a determining circuit. The power detecting circuit may generate a plurality of detection signals based on a plurality of sensing signals corresponding to currents flowing through a plurality of function blocks. The selecting circuit may generate a plurality of selection signals. The determining circuit may generate a power-up completion signal and a power-down completion signal. A semiconductor device having the power-up/power-down detecting circuit may determine in real time the power-up time and the power-down time.

Circuit of detecting power-up and power-down

A test apparatus capable of detecting input/output (I/O) circuit characteristics of a semiconductor device by analyzing an eye mask generated in the test apparatus and the waveform of a test signal output from the I/O circuit of the semiconductor device. The test apparatus includes an eye mask generator that generates an eye mask in synchronization with one or more clock signals of opposite phase to each other, an error detector that receives the eye mask from the eye mask generator and compares the test signal with the eye mask to determine whether an error occurs in the semiconductor device, and an error signal output unit that receives an error detection signal from the error detector and generates an error signal in response to the error detection signal. In particular, the eye mask generator includes a sine wave generator that generates one or more sine waves of opposite phase to each other in synchronization with one or more clock signals, and a limiter circuit that receives the sine waves and generates the eye mask by adjusting the amplitudes of the sine waves.

Apparatus and method for testing circuit characteristics by using eye mask

A semiconductor driver circuit includes impedance units for generating impedances at data pads, independently of each-other. Thus, signal swing widths of data signals generated at the data pads may be easily adjusted to be substantially equal for high operating speed. The semiconductor driver circuit also includes switching units for uncoupling at least one of the impedance units from at least one of the data pads for enhanced testing of the data pads.

Semiconductor driver circuit with signal swing balance and enhanced testing

Provided are a semiconductor device, a test board, and a test system and method for testing a semiconductor device. The semiconductor device includes an input terminal to which test pattern data is serially input at a first speed and an output terminal which one-to-one corresponds to the input terminal and serially outputs the test pattern data to the outside at a second speed that is different from the first speed.

Semiconductor device, test board for testing the same, and test system and method for testing the same

The present invention provides a high-speed memory device that can be easily tested using the existing low-speed Automatic Test Equipment (ATE). In an embodiment of the invention, a memory device includes two channels. During normal communications with a host, one channel is used for bi-directional communications with a host. But during a test mode, a first channel is used to communicate with the ATE in one direction, and a second channel is used to communicate with the ATE in the opposite direction. The present invention also provides a memory module and a method for controlling the high-speed memory device.

High-speed memory device easily testable by low-speed automatic test equipment and input/output pin control method thereof

A socket for an electrical tester is disclosed. The socket includes a first contact board being arranged at a bottom side of a test object, and a second contact board being arranged at a top side of the test object. The first contact board includes a first contact member and a first conductive connection member, wherein the first contact member is electrically connected to a bottom connection terminal formed on the bottom side of the test object, and the first conductive connection member is isolated from the test object. The second contact board includes a second contact member, wherein the second contact member is electrically connected to the first conductive connection member and a top connection terminal formed on a top side of the test object, respectively. Therefore, the socket can have a simple configuration for providing the test current.

Socket for an electrical tester

A stack-type semiconductor package socket may include: a first package connection portion for connection with leads of a lowermost package of a stack-type semiconductor package; a second package connection portion for connection between pads of an odd-numbered package and leads of an even-numbered package, wherein the odd-numbered package and the even-numbered package are adjacent to each other; a lower case for fixing the first package connection portion; and an upper case for fixing the second package connection portion. A stack-type semiconductor package test system may include: a stack-type semiconductor package socket that includes first and second package connection portions; a printed circuit board electrically connected to leads of the lowermost package through the first package connection portion; and a test controller for receiving, outputting, or receiving and outputting signals from, to, or from and to the stack-type semiconductor package through the PCB and the stack-type semiconductor package socket.

Stack-type semiconductor package sockets and stack-type semiconductor package test systems

Method and apparatus for use with simultaneous bi-directional (SBD) input/output circuits are included among the embodiments. In exemplary systems, the receiver in an SBD circuit compares a bit line voltage to two different voltages representing the two voltages that are expected on the bit line, based on the data that the driver in the SBD circuit is currently driving. Other embodiments are described and claimed.

Simultaneous bidirectional input/output circuit and method

A high-speed disturb testing method for a semiconductor memory device is disclosed, includes the steps of: (a) writing first piece of data in all of the memory cells in the memory cell array; (b) reading and confirming the first piece data written in each memory cell of the memory cell array; (c) writing second piece data in all of the memory cells connected to the plurality of disturb word lines; (d) reading and confirming the second piece data from all of the memory cells (e) fixing the mode of the disturb word line to the test mode; (f) repeatedly writing the second piece data in all of the memory cells connected to the plurality of disturb word lines; (g) changing the test mode to the normal mode; (h) refreshing all of the memory cells; (i) reading and confirming the first piece data from a word line located close to the selected plurality of disturb word lines; (j) writing the first piece data in all of memory cells connected to the plurality of disturb word lines; (k) repeating the steps (3) to (10), to thereby apply disturb to all of the word lines one by one; and (l) reading and confirming the first piece data from the memory cell array.

Growing community of inventors

Seoul, South Korea

Woo-seop Kim