Samsung Electronics Co., Ltd.

Woo-seop Jeong

Byung-Chul Kim

Byung-Hoon Jeong

Hyun-Soon Jang

Kyung-ho Kim

Han-gu Sohn

Sei-jin Kim

Yong-Cheol Bae

Jae-yoon Sim

Gyu-hong Kim

Hai-jeong Sohn

Beob-Rae Cho

Seung-Bum Ko

Jong-bok Tcho

Sung-ryul Kim

Sung-geun Lee

Circuits and methods for controlling data I/O operations in semiconductor memory devices to provide variable data I/O widths for read, write and active memory operations. Circuits and methods for selectively controlling a data width of a data I/O buffer 'on the fly' to enable variable data I/O widths during memory access operations.

Circuits and methods for providing variable data I/O width for semiconductor memory devices

A memory device, such as a DDR SDRAM, may be provided in which subsets of data output circuits of the device can be selectively enabled to allow sets of data output pins to be connected in common in a testing configuration. In some embodiments, a memory device includes a plurality of data output circuits, respective ones of which are configured to receive data from respective internal data lines and respective ones of which are coupled to respective data input/output pins. The device further includes a data output control circuit operative to selectively enable subsets of the plurality of data output circuits to drive their respective corresponding data input/output pins responsive to an externally-applied control signal. The data output control circuit may be operative to selectively cause subsets of the plurality of data output circuits to present a high impedance at their respective corresponding data input/output pins. The invention may be embodied as devices and methods.

Memory devices with selectively enabled output circuits for test mode and method of testing the same

Provided are a synchronous semiconductor device having constant data output time regardless of a bit organization, and a method of adjusting data output time. The synchronous semiconductor device includes an internal clock generator for receiving an external clock and generating an internal clock, a clock controller for adjusting the phase of the internal clock and generating a data output clock in response to bit organization information, and a data output buffer for outputting data read from a memory cell to the outside in response to the data output clock. Thus, it is possible to prevent vertical vibration in a disc loaded in a disc driver regardless of wobble of the disc.

Synchronous semiconductor device having constant data output time regardless of bit organization, and method of adjusting data output time

A data input circuit for a synchronous semiconductor memory device may comprise a detection unit for detecting whether the phase of a data strobe signal may lead or lag that of a clock signal. A delay unit may delay the data strobe signal by a first duration when the phase of the data strobe signal leads that of the clock signal and may delay the data strobe signal by a second duration when the phase of the data strobe signal lags that of the clock signal. A data input unit may synchronize a first input data signal previously fetched by the data strobe signal to the clock signal in response to an output signal of the delay unit. The data input circuit may effectively synchronize an input data signal using an internal delay that may be adjusted when a frequency of the clock signal may exceed a predetermined threshold.

Data input circuits and methods of inputting data for a synchronous semiconductor memory device

A semiconductor integrated circuit includes a sense amplifier for amplifying an input signal and an complementary input signal, a full differential amplifier for amplifying the output of the sense amplifier, and a latch for latching the output of the full differential amplifier and outputting the latched output. The full differential amplifier includes a first differential amplifying unit for increasing the voltage of an output port when the level of an input signal input through an input port is larger than the level of an complementary input signal input through an complementary input port and reducing the voltage of the output port when the level of the input signal is lower than the level of the complementary input signal, a second differential amplifying unit for reducing the voltage of an complementary output port when the level of the input signal is larger than the level of the complementary input signal and increasing the voltage of the complementary output port when the level of the input signal is lower than the level of the complementary input signal, and an output voltage level control circuit connected between the output port and the complementary output port. The output voltage level control circuit controls the voltage levels of the output signals output from the output port and the complementary output port. The sense amplifier can stabilize the operation of the latch by reducing the mean voltage level of the output signal even when the supply A voltage increases, can easily control the voltage gain of the full differential amplifier by controlling the resistance, and stably operates at high speed. The current sense amplifier can include resistors associated with PMOS transistors to avoid unstable operation caused by increased transconductance arising from higher operating voltage.

Sense amplifier of semiconductor integrated circuit

An integrated circuit memory device includes a DQM input buffer controller that enables the DQM buffer to process the DQM mask signal during a row active period of a read operation and a write operation of an integrated circuit memory device, and during a latency period of the read operation and the write operation, and that disables the DQM buffer otherwise during the read operation and the write operation. Thus, the DQM buffer is enabled to process the DQM mask signal during those portions of the read and write operations in which the external DQM mask signal is received and the DQM buffer is otherwise disabled during the read and write operations. The controller can also disable the DQM buffer during a refresh operation of the memory device and a power-down operation of the memory device. Accordingly, reduced current consumption in the DQM buffers may be obtained by only enabling the DQM input buffers when a DQM mask signal is expected during the read and write operations of the memory device.

Memory device having a controller capable of disabling data input/output mask (DQM) input buffer during portions of a read operation and a write operation

An internal clock generation circuit for a semiconductor device and a method for generating an internal clock signal are disclosed. The internal clock generation circuit reduces the power consumed by a semiconductor device by generating internal clock pulses only when they are necessary for the operation of the device. The internal clock generation circuit includes a clock buffer, an internal clock generation unit, a chip selection buffer and an internal clock control unit. The clock buffer converts the voltage level of an external clock signal. The internal clock generation unit receives the output from the clock buffer and generates an internal clock signal only when a control signal is enabled. The chip selection buffer converts the voltage level of a chip selection signal which is active when the device is enabled. The internal clock control unit receives the output from the chip selection buffer and generates the control signal which is activated when the chip selection signal is active. The internal clock control unit also activates the control signal when either a column address signal or a latency signal is enabled. The internal clock signal is disabled when the control signal is disabled, and enabled when the control signal is enabled and at the same time the external clock signal is enabled.

Internal clock generation circuit of semiconductor device and method for

A clock signal generating circuit for use in a synchronous dynamic random access memory device. The clock signal generating circuit includes an input buffer for converting an externally supplied system clock signal having a first voltage level into a clock signal having a voltage level necessary for operating with the internal circuitry of the memory device. An enable path circuit generates a second transition of an internal clock signal which occurs substantially simultaneous the second transition of the system clock signal. The enable path circuit generates the first transition of the internal clock signal after the internal clock signal is maintained at the second state for a predetermined interval responsive to first and second disable signals. Finally, a disable path circuit receives the clock signal generated from the input buffer and supplies the first and second disable signals to the enable path circuit.

Dynamic clock signal generating circuit for use in synchronous dynamic

Methods and apparatus for controlling output buffer circuitry in a synchronous semiconductor memory device. An internal clock signal is generated and logic provided to provide a control signal that enables that output buffer circuitry for a read operation. An internal clock signal is generated synchronized to the external or system clock signal. An intermediate control signal is triggered by the internal clock signal at a selected number of cycles less than the memory latency period after a read command, and then the control signal for enabling the output buffer is asserted on a subsequent cycle of the internal clock signal, thereby ensuring at least a predetermined minimum time for the output buffer control signal to propagate through the memory device before data is transferred out of the device.

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Kyungki-do, South Korea

Woo-seop Jeong