Samsung Electronics Co., Ltd.

Woo-Pyo Jeong

Sang-Wan Nam

Jae-Hoon Lee

Ho-Young Kim

Jong-Hoon Lee

Eun-Suk Cho

Yong-Gyu Chu

Seouk-Kyu Choi

Jung-ho Song

Yun-Ho Hong

A non-volatile memory device includes a memory cell array region in which memory cells are vertically stacked on a substrate and a page buffer region in which first and second page buffers are arranged. A first distance between the memory cell array region and the first page buffer is shorter than a second distance between the memory cell array region and the second page buffer. The first page buffer includes a first transistor driven in response to a first control signal. The second page buffer includes a second transistor driven in response to a second control signal corresponding to the first control signal. At least one of design constraints and processing constraints with respect to the first and second transistors is different.

Non-volatile memory device having page buffers with differing characteristics

A multi-channel semiconductor memory device and a method of refreshing the same. In the multi-channel semiconductor memory device and method, a common refresh controller is prepared to detect refresh operation states of a plurality of sub-memory circuits (e.g. ICs) and to adjust refresh operation times of multiple sub-memory ICs so that two or more sub-memory ICs do not simultaneously perform a refresh operation, thereby reducing the peak current.

Multi-channel semiconductor memory device and method of refreshing the same

A precharge method of a semiconductor memory device that controls a precharge start time of each bank during a bank precharge operation, and a semiconductor memory device using the method, are provided. The device may latch an active or write order of respective banks and differently control precharge start times of the respective banks according to the latched active or write order during a plural-bank precharge operation to allow a plurality of banks to start precharge operations at different times.

Precharge method of semiconductor memory device and semiconductor memory device using the same

Provided is a semiconductor package and method of manufacturing same. The method includes: forming a plurality of semiconductor chips which have the same pattern direction on a semiconductor substrate, each of which includes a memory cell region, a peripheral region and a pad region, and in each of which the pad region is disposed in an edge region; separating the semiconductor chips, which are formed on the semiconductor substrate, from one another; and disposing semiconductor chips, which are selected from the separated semiconductor chips, on a package substrate by changing the pattern directions of the selected semiconductor chips and arranging pad regions of the selected semiconductor chips in a center region of the package substrate.

Method of manufacturing semiconductor package

A semiconductor memory device and a related method are disclosed. The semiconductor memory device includes a data sensing output unit simultaneously providing first and second data to first and second data path lines, respectively; and a data output circuit, wherein the first and second data are serially output to an output terminal through the data output circuit. The device further includes a data transmitter operationally connecting the first data path line to the data output circuit and operationally connecting the second data path line to the data output circuit; and a data path controller connected between the data sensing output unit and the data transmitter, delaying the second data, and including first and second delay elements, wherein each of the first and second delay elements is disposed along one of the first and second data path lines.

Semiconductor memory device comprising data path controller and related method

A first voltage generator generates an active power voltage at a first power line having a decoupling capacitor coupled thereto. A second voltage generator generates a standby power voltage at a second power line. A switch is coupled between the first and second power lines. The switch is closed and the second voltage generator is disabled for an active mode of operation. The decoupling capacitor speeds up charging of the second power line to the active power voltage.

Apparatus and method for supplying power voltages in active and stand-by modes

A memory device includes a first sensing amplifier to amplify data received from the memory array, a first driver to generate a first tri-state signal responsive to the amplified data from an first sense amplifier and to provide the first tri-state signal to a data bus line, a second sensing amplifier to amplify data received from the memory array, and a second driver to generate a second tri-state signal responsive to the amplified data from an second sense amplifier and to provide the second tri-state signal to the data bus line, where the first sensing amplifier and the first driver are located in different regions of the device, and the second sensing amplifier and the second driver are located in a common region of the device.

Growing community of inventors

Seoul, South Korea

Woo-Pyo Jeong