Samsung Electronics Co., Ltd.

Samsung Sdi Co., Inc.

Infineon Technologies Ag

Woo Jin Jang

Jin Su Park

Seung Hyun Oh

Bio Kim

Young Jin Noh

Kyong Won An

Jun Kyu Yang

Jae Hoon Lee

Sang Ho Lee

Jong Woo Lee

Tae Sik Kim

Bum Ki Moon

Yong Gyu Lim

Jun Ho Chung

Hyung Woo Kim

Sung Dong Cho

Yun Gi Kim

Bong Hyun Cho

Hun Young Park

An analog-to-digital converter includes a comparator configured to compare an input signal with a reference signal and to output a comparison signal indicating a corresponding comparison result, a control logic configured to output a control signal for adjusting the reference signal based on the comparison signal, and a reference signal adjusting circuit configured to adjust the reference signal based on the control signal. The comparator includes a first pre-amplifier configured to amplify a difference between the input signal and the reference signal using a first transistor having a first size, a second pre-amplifier configured to amplify the difference between the input signal and the reference signal using a second transistor having a second size different from the first size, and a latch configured to generate the comparison signal using at least one of an output of the first and second pre-amplifiers. The first and second pre-amplifiers share the latch.

Analog-to-digital converter and method of performing analog-to-digital conversion

An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.

Integrated circuit memory devices having impurity-doped dielectric regions therein and methods of forming same

A bandgap reference voltage generation system includes a common mode voltage generator, a bandgap reference voltage generation circuit, and a switch controller. The bandgap reference voltage generation circuit includes a plurality of transistors having source terminals respectively connected to drain terminals of a plurality of PMOS transistors. The switch controller provides a ground voltage to the bandgap reference voltage generation circuit in a first mode and a common mode voltage to the bandgap reference voltage generation circuit in a second mode. The bandgap reference voltage generation circuit causes the plurality of the transistors to operate in a linear region by providing the common mode voltage to gate electrodes of the plurality of the transistors in the first mode and a saturation region by providing the ground voltage to the gate electrodes of the plurality of the transistors in the second mode.

Bandgap reference voltage generation circuit and bandgap reference voltage generation system

Provided are an apparatus and method for coating a separator. The method includes supplying a coating solution to a receiving chamber; applying the coating solution received in the receiving chamber to a surface of the separator through a coating bar; collecting coating solution overflowing the receiving chamber by a collection chamber surrounding the receiving chamber; and returning coating solution from the collection chamber to the receiving chamber through a return line.

Apparatus for coating a separator having collection chamber and method for coating the separator

A drying apparatus that dries a porous membrane that is carryable along a predetermined direction and a drying method, the drying apparatus including a housing; a plurality of air suppliers arranged in the housing along the predetermined direction so as to inject air toward the porous membrane; and a plurality of air exhausters arranged in the housing along the predetermined direction so as to exhaust air that has been injected from the air suppliers to an exterior of the housing, wherein the plurality of air suppliers are symmetrically arranged with one another at opposite sides of the porous membrane to face each other with the porous membrane disposable therebetween.

Apparatus and method for drying

Methods of forming electrical interconnects include forming a copper pattern on a semiconductor substrate and then forming an electrically insulating capping layer on the copper pattern and an interlayer insulating layer on the electrically insulating capping layer. A contact hole is then formed, which extends through the interlayer insulating layer and the electrically insulating capping layer and exposes an upper surface of the copper pattern. An electroless plating step is then performed to form a copper pattern extension onto the exposed upper surface of the copper pattern. The copper pattern extension may have a thickness that is less than a thickness of the electrically insulating capping layer, which may be formed as a SiCN layer.

Methods of forming electrical interconnects using electroless plating techniques that inhibit void formation

Growing community of inventors

Suwon-si, South Korea

Woo Jin Jang