International Business Machines Corporation

Advanced Micro Devices Corporation

Applied Materials, Inc.

Woo-Hyeong Lee

Judson Robert Holt

Yun-Yu Wang

Vijay Narayanan

Cyril Cabral, Jr

Ying Li

Ashima B Chakravarti

Diane Catherine Boyd

Anda C Mocuta

An L Steegen

Richard D Kaplan

Jakub Tadeusz Kedzierski

Victor Ku

Ricky S Amos

Huilong Zhu

Renee Tong Mo

Scott D Luning

Christopher D Sheraw

Michael Abramovich Gribelyuk

Anita Madan

Daewon Yang

Linda R Black

Tai-chi Su

Ryan Matthew Mitchell

Maheswaren Surendra

Kangguo Cheng

Bruce Bennett Doris

Oleg Gluschenkov

Kevin K Chan

Amlan Majumdar

Omer H Dokumaci

Henry K Utomo

Byeong Yeol Kim

Huajie Chen

Werner A Rausch

Zhibin Ren

Maheswaran Surendra

Dan Mihai Mocuta

Xiaomeng Chen

Paul Andrew Ronsheim

Dinkar Virendra Singh

Murshed Mahmud Chowdhury

Suk Hoon Ku

Jeremy John Kempisty

Ramaseshan Suryanarayanan Iyer

Aimin Xing

Romany Ghali

Gregory Wayne Dibello

Embodiments of the present invention provide an improved method for forming transistor contacts. A sacrificial layer is deposited in a first set of contact cavities, and a capping layer is formed on the sacrificial layer. This protects the first set of contact cavities during formation of a second set of contact cavities. The sacrificial layer is then removed, and the first and second sets of contact cavities are filled with a conductive material.

Method of forming transistor contacts

An intermediate hybrid surface orientation structure may include a silicon-on-insulator (SOI) substrate adhered to a bulk silicon substrate, the silicon of the SOI substrate having a different surface orientation than that of the bulk silicon substrate, and a reachthrough region extending through the SOI substrate to the bulk silicon substrate, the reachthrough region including a silicon nitride liner over a silicon oxide liner and a silicon epitaxially grown from the bulk silicon substrate, the epitaxially grown silicon extending into an undercut into the silicon oxide liner under the silicon nitride liner, wherein the epitaxially grown silicon is substantially stacking fault free.

Stacking fault reduction in epitaxially grown silicon

Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8 W/cmand 5.0 W/cm; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.

Compressive nitride film and method of manufacturing thereof

A pair of semiconductor structures and a method for fabricating a semiconductor structure each utilize a semiconductor substrate having a first crystallographic orientation, and a dielectric layer located thereupon. The method provides for epitaxially growing a semiconductor layer on the semiconductor substrate to encapsulate the dielectric layer. The method also provides for patterning the semiconductor layer to yield a semiconductor structure that comprises a bulk semiconductor structure and a semiconductor-on-insulator structure, or alternatively a patterned semiconductor layer that straddles the dielectric layer and contacts the semiconductor substrate.

Semiconductor substrate with multiple crystallographic orientations

A semiconductor fabrication method. The method includes providing a semiconductor substrate, wherein the semiconductor substrate includes a semiconductor material. Next, a top portion of the semiconductor substrate is removed. Next, a first semiconductor layer is epitaxially grown on the semiconductor substrate, wherein a first atomic percent of a first semiconductor material in the first semiconductor layer is equal to a substrate atomic percent of the substrate semiconductor material in the semiconductor substrate.

Method for improving semiconductor surfaces

Methods and resulting structure of forming a transistor having a high mobility channel are disclosed. In one embodiment, the method includes providing a gate electrode including a gate material area and a gate dielectric, the gate electrode being positioned over a channel in a silicon substrate. A dielectric layer is formed about the gate electrode, and the gate material area and the gate dielectric are removed from the gate electrode to form an opening into a portion of the silicon substrate that exposes source/drain extensions. A high mobility semiconductor material, i.e., one having a carrier mobility greater than doped silicon, is then formed in the opening such that it laterally contacts the source/drain extensions. The gate dielectric and the gate material area may then be re-formed. This invention eliminates the high temperature steps after the formation of high mobility channel material used in related art methods.

Transistor having high mobility channel and methods

Methods are disclosed for providing stacking fault reduced epitaxially grown silicon for use in hybrid surface orientation structures. In one embodiment, a method includes depositing a silicon nitride liner over a silicon oxide liner in an opening, etching to remove the silicon oxide liner and silicon nitride liner on a lower surface of the opening, undercutting the silicon nitride liner adjacent to the lower surface, and epitaxially growing silicon in the opening. The silicon is substantially reduced of stacking faults because of the negative slope created by the undercut.

The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

CMOS silicide metal gate integration

A strained HOT MOSFET fabrication method. The MOSFET fabrication method includes providing a semiconductor structure which includes (a) a first semiconductor layer having a first crystallographic orientation, (b) a buried insulating layer on top of the first semiconductor layer, (c) a second semiconductor layer on top of the buried oxide layer. The second semiconductor layer has a second crystallographic orientation different from the first crystallographic orientation. The method further includes forming a third semiconductor layer on top of the first semiconductor layer which has the first crystallographic orientation. The method further includes forming a fourth semiconductor layer on top of the third semiconductor layer. The fourth semiconductor layer (a) comprises a different material than that of the third semiconductor layer, and (b) has the first crystallographic orientation.

Strained HOT (hybrid orientation technology) MOSFETs

A method of forming polycrystalline silicon with ultra-small grain sizes employs a differential heating of the upper and lower sides of the substrate of a CVD apparatus, in which the lower side of the substrate receives considerably more power than the upper side, preferable more than 75% of the power; and in which the substrate is maintained during deposition at a temperature more than 50&#xb0; C. above the 550&#xb0; C. crystallization temperature of silicon.

Polycrystalline silicon layer with nano-grain structure and method of manufacture

A compound that includes at least Si, N and C in any combination, such as compounds of formula (R&#x2014;NH)SiXwherein R is an alkyl group (which may be the same or different), n is 1, 2 or 3, and X is H or halogen (such as, e.g., bis-tertiary butyl amino silane (BTBAS)), may be mixed with silane or a silane derivative to produce a film. A polysilicon silicon film may be grown by mixing silane (SiH) or a silane derviative and a compound including Si, N and C, such as BTBAS. Films controllably doped with carbon and/or nitrogen (such as layered films) may be grown by varying the reagents and conditions.

Deposition of carbon and nitrogen doped poly silicon films, and retarded boron diffusion and improved poly depletion

The present invention provides a method for retarding the diffusion of dopants from a first material layer (typically a semiconductor) into an overlayer or vice versa. In the method of the present invention, diffusion of dopants from the first semiconductor into the overlayer or vice versa is retarded by forming a monolayer comprising carbon and oxygen between the two layers. The monolayer is formed in the present invention utilizing a chemical pretreatment process in which a solution including iodine and an alcohol such as methanol is employed.

Chemical treatment to retard diffusion in a semiconductor overlayer

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Poughquag, NY, United States of America

Woo-Hyeong Lee