Samsung Display Co., Ltd.

Samsung Electronics Co., Ltd.

Other

Woo-Geun Lee

Ki-Won Kim

Young-Wook Lee

Kap-Soo Yoon

Hye-Young Ryu

Jae-Hyoung Youn

Seung-Ha Choi

Hyun-Jung Lee

Je-Hun Lee

Do-Hyun Kim

Jang-Soo Kim

Sang-Gab Kim

Shi-Yul Kim

Ji-Soo Oh

Pil-Sang Yun

Young-Joo Choi

Kyoung-Jae Chung

Sung-Hoon Yang

Min-Seok Oh

Hong-Kee Chin

Jean-Ho Song

Sang-Woo Whangbo

Hee-Jun Byeon

Jong-in Kim

Jin-Won Lee

Jong-In Kim

Dong-Ju Yang

Sung-Haeng Cho

Chang-Oh Jeong

Ki-Hun Jeong

Yu-Gwang Jeong

Jin-Ho Ju

Bong-Kyun Kim

Shin-Il Choi

Byeong-Beom Kim

Seung-Hwan Shim

Hong-Suk Yoo

Hong-Sick Park

Jong-Hyun Choung

Yeong-Keun Kwon

Byeong-Jin Lee

Sun-Young Hong

Sung-Ryul Kim

Jung-In Park

Yang-Ho Bae

Nam-Seok Suh

Ji-Yun Hong

Hong-Long Ning

Xun Zhu

Jang-Hoon Ha

Dong-Hoon Lee

Chong-Chul Chai

Hoon Jong Kang

Hyang-Shik Kong

Sang-Hun Lee

Mee-Hye Jung

Yang-Ho Jung

Beom-Seok Cho

Young-Je Cho

Jae-Sung Kim

Sang-Ki Kwak

Yun-Seok Lee

Woo-Seok Jeon

Byung-Duk Yang

Min-cheol Lee

Hee-Hwan Choe

Jun-Hyung Souk

Je-Hyeong Park

Won-Kie Chang

Cheon-Jae Maeng

Jae-Woo Park

Jae-Hyoung Yoon

Youn-Hee Cha

A substrate including a first signal line and a first electrode disposed on the substrate, an oxide semiconductor layer pattern overlapping the first electrode, an insulating layer disposed between the first electrode and the oxide semiconductor layer pattern, a second signal line intersecting the first signal line, a second electrode electrically connected to the oxide semiconductor layer pattern, a third electrode electrically connected to the oxide semiconductor layer pattern and spaced apart from the second electrode, and an insulator comprising a first portion disposed between the first signal line and the second signal line, and at least partially overlapping with both of the first signal line and the second signal line.

Thin film transistor array substrate and manufacturing method thereof

A substrate including a gate line and a first electrode disposed on the substrate, an oxide semiconductor layer pattern overlapping the first electrode, an insulating layer disposed between the first electrode and the oxide semiconductor layer pattern, a data line intersecting the gate line, a second electrode electrically connected to the oxide semiconductor layer pattern, a third electrode electrically connected to the oxide semiconductor layer, the third electrode spaced apart from the second electrode, and an insulating pattern including a first portion which is disposed between the gate line and the data line and at least partially overlaps with both of the gate line and the data line.

A substrate including a gate line and a gate electrode disposed on a substrate, an oxide semiconductor layer pattern overlapping the gate electrode, a gate insulating layer disposed between the gate electrode and the oxide semiconductor layer pattern, a data line intersecting the gate line, a source electrode electrically connected to the oxide semiconductor layer pattern, a drain electrode electrically connected to the oxide semiconductor layer, the drain electrode spaced apart from the source electrode, and an insulating pattern including a first portion, which is disposed between the gate line and the data line and at least partially overlaps with both of the gate line and the data line.

A substrate including gate wirings including a gate line and a gate electrode disposed on a substrate, an oxide semiconductor layer pattern overlapping the gate electrode, a gate insulating layer disposed between the gate wirings and the oxide semiconductor layer pattern, data wirings including a data line crossing the gate line, a source electrode connected to one side of the oxide semiconductor layer pattern, and a drain electrode connected to another side of the oxide semiconductor layer, and an insulating pattern including a first portion which is disposed between the gate line and the data line and at least partially overlaps with both of the gate line and the data line.

A TFT array substrate includes a semiconductive oxide layer disposed on an insulating substrate and including a channel portion, a gate electrode overlapping the semiconductive oxide layer, a gate insulating layer interposed between the semiconductive oxide layer and the gate electrode, and a passivation layer disposed on the semiconductive oxide layer and the gate electrode. At least one of the gate insulating layer and the passivation layer includes an oxynitride layer, and the oxynitride layer has a higher concentration of oxygen than that of nitrogen in a location of the oxynitride layer closer to the semiconductive oxide layer.

Thin film transistor array substrate and method of manufacturing the same

A substrate including gate wirings including gate line and a gate electrode disposed on the substrate, a storage line disposed on the same layer as the gate wirings, a gate insulating layer disposed on the gate wirings and the storage line, an oxide semiconductor layer pattern disposed on the gate insulating layer, data wirings including a data line crossing the gate line, a source electrode disposed on one side of the oxide semiconductor layer pattern, and a drain electrode disposed on another side of the oxide semiconductor layer, and an etch stopper including a first etch stopper portion disposed between the storage line and the data line and partially overlapping both the data line and the storage line.

A Thin Film Transistor (TFT) includes a substrate, a semiconductor layer disposed on the substrate a first source electrode and a first drain electrode spaced apart from each other on the semiconductor layer, a channel area disposed in the semiconductor layer between the first source electrode and the first drain electrode, an etching prevention layer disposed on the channel area, the first source electrode, and the first drain electrode and a second source electrode in contact with the first source electrode, and a second drain electrode in contact with the first drain electrode.

Thin film transistor, thin film transistor panel, and method for manufacturing the same

A method of manufacturing a thin film transistor (TFT) array substrate includes forming a gate line and a gate electrode on a substrate, forming a gate-insulating layer and an oxide semiconductor layer on the gate line and the gate electrode, forming etch stop patterns at a thin-film transistor area and an area where the gate line and the data line overlap each other, forming a data conductor on the oxide semiconductor layer and the etch stop patterns, the data conductor comprising a source electrode and a drain electrode that constitute a TFT together with the gate electrode, and forming a data line extending in a direction intersecting the gate line.

A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

Thin film transistor panel having an etch stopper on semiconductor

Provided are a display substrate, a display device, and a method of manufacturing the display substrate. The display substrate includes: a substrate in which a pixel region is defined; a gate electrode and a gate pad are formed on the substrate; a gate insulating layer formed on the gate electrode and the gate pad; a buffer layer pattern overlaps the gate electrode and is formed on the gate insulating layer; an insulating film pattern formed on the buffer layer pattern; an oxide semiconductor pattern formed on the insulating film pattern; a source electrode formed on the oxide semiconductor pattern; and a drain electrode formed on the oxide semiconductor pattern and is separated from the source electrode.

Method of manufacturing a display substrate using two etch masks

A TFT display panel having a high charge mobility and making it possible to obtain uniform electric characteristics with respect to a large-area display is provided as well as a manufacturing method thereof. A TFT display panel includes a gate electrode formed on an insulation substrate, a first gate insulting layer formed of SiNx on the gate electrode, a second gate insulting layer formed of SiOx on the first gate insulting layer, an oxide semiconductor layer formed to overlap the gate electrode and having a channel part, and a passivation layer formed of SiOx on the oxide semiconductor layer and the gate electrode, and the passivation layer includes a contact hole exposing the drain electrode. The contact hole has a shape in which the passivation layer of a portion directly exposed together with a metal occupies an area smaller than the upper passivation layer.

Thin film transistor display panel and manufacturing method of the same

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Yongin-si, South Korea

Woo-Geun Lee