Micron Technology Incorporated

Wonjun Choi

Kang-Yong Kim

Yang Lu

Hiroshi Akamatsu

Kenji Yoshida

Jacob Rice

Apparatuses and techniques for implementing a data sense amplifier circuit with a hybrid architecture. With the hybrid architecture, the data sense amplifier circuit includes a first set of amplifiers that are shared by multiple banks and includes a second set of amplifiers with multiple subsets dedicated to different banks. The bank-shared amplifiers support memory operations (e.g., a read operation) across multiple banks. Each amplifier within the first set of amplifiers is coupled to at least two banks. The bank-specific amplifiers support usage-based disturbance mitigation for a corresponding bank. Each amplifier within the second set of amplifiers is coupled to one of the multiple banks. The bank-shared amplifiers enable the data sense amplifier circuit to have a smaller footprint while the bank-specific amplifiers enable the data sense amplifier circuit to support usage-based disturbance mitigation and avoid conflicts associated with some sequences of commands.

Data sense amplifier circuit with a hybrid architecture

An example apparatus may perform concurrent threshold voltage compensation in a memory array with distributed row redundancy. The example apparatus may include a memory cell array having a mat having a plurality of row sections that each include respective prime memory cell rows and a respective redundant memory cell row. The example apparatus may further include a row decoder configured to receive an access command and a prime row address. The row decoder may be configured to, in response to a determination that the prime row address matches a defective prime row address, concurrently initiate a threshold voltage compensation operation on both of a prime row of the respective plurality of prime rows of memory cells of a first row section of the plurality of row sections corresponding to the prime row address and the respective redundant row of a second row section of the plurality of row sections.

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Boise, ID, United States of America

Wonjun Choi