Samsung Electronics Co., Ltd.

Wonjae Shin

Insu Choi

Dae-Jeong Kim

Sung-Joon Kim

Yongjun Yu

Minsu Kim

Changmin Lee

Deokho Seo

Chanik Park

Do-Han Kim

Dohan Kim

Namhyung Kim

Tae-Kyeong Ko

Daejeong Kim

Nam Hyung Kim

Ilguy Jung

Jiseok Kang

Wooseop Kim

Doohwan Oh

Minsoo Kim

Donghoon Lee

Ho-Young Reho Lee

Young-hwan Kim

Kwanghee Lee

Hyuncheol Park

Jae-Hyon Kim

Heedong Kim

Do-han Kim

Jongyoung Lee

Mijin Lee

Yeonhwa Lee

Seung Ju Lee

Kideok Han

Hyunkuk Kim

Hui-Chung Byun

Byungjik Kim

Eunbyeol Ko

Ilwoong Seo

Minsu Bae

Youjin Jang

Hyan Suk Lee

Sung-joon Kim

A method of operating a storage module, the method including setting a characteristic value based on information received from a host, the information including information related to a size of write data in units of cache lines, and successively receiving the write data in units of the cache lines based on a single write command received from the host.

Storage module supporting single serialized write interfacing scheme and operation method thereof

A method of operating the storage module includes setting a characteristic value based on information on a prefetch size received from a host, and performing consecutive read operations in units of cache lines based on one prefetch read command received from the host.

Storage module supporting prefetch function and operation method thereof

A memory system includes a memory module that includes a first memory device through a fourth memory device and a first error correction code (ECC) device, and a memory controller that exchanges first user data with each of the first memory device through the fourth memory device through 8 data lines and exchanges first ECC data with the first ECC device through 4 data lines. The memory controller includes an ECC engine that corrects a 32-random bit error of the first user data, based on the first ECC data.

Memory module, memory system, and operation method of memory controller

An operation method of a memory device, having a plurality of memory cells, includes receiving a partial write command, which includes a partial write enable signal (PWE) and a plurality of mask signals, during a command/address input interval. A data strobe signal is received through a data strobe line after receiving the partial write command Data is received through a plurality of data lines in synchronization with the data strobe signal during a data input interval. A part of the data is stored in the plurality of memory cells based on the plurality of mask signals, in response to the partial write enable signal, during a data write interval.

Electronic device, operation method of host, operation method of memory module, and operation method of memory device

A memory device includes a memory cell array and a test controller. The memory cell array includes a plurality of memory cells, where the memory cell array is divided into multiple regions. The test controller is configured to perform a parallel bit test (PBT) on the plurality of memory cells, where the test controller selects fail data including a fail data bit among internal data output from the multiple regions during the PBT, and outputs the fail data via a data input/output signal line to the outside of the memory device.

Memory device capable of outputting fail data in parallel bit test and memory system including the memory device

Provided are an accelerator controlling a memory device, a computing system including the accelerator, and an operating method of the accelerator. The accelerator includes: a signal control/monitoring circuit configured to detect an entry to a self-refresh mode of a memory device and an exit from the self-refresh mode based on monitoring a signal provided from a host; an accelerator logic configured to generate a first command/address signal and a first piece of data; and a selector configured to output the first command/address signal and the first piece of data to the memory device based on detection of the entry to the self-refresh mode, and output a second command/address signal and a second piece of data provided from the host, to the memory device, based on detection of the exit from the self-refresh mode.

Accelerator controlling memory device, computing system including accelerator, and operating method of accelerator

Provided are a memory device skipping a refresh operation and an operating method thereof. The memory device includes a memory cell array including N rows; a refresh controller configured to control a refresh operation for the N rows of the memory cell array based on a refresh command; and an access information storage circuit including a plurality of registers configured to store flag information corresponding to each of the N rows, wherein a first value indicates rows that have been accessed, and a second value indicates rows that have not been accessed. The refresh controller is further configured to control whether the refresh operation is performed for a first row of the N rows at a refresh timing for the first row based on the flag information corresponding to the first row.

Memory device skipping refresh operation and operation method thereof

A method for accessing a memory module includes; encoding first data of a first partial burst length to generate first parities and first cyclic redundancy codes, encoding second data of a second partial burst length to generate second parities and second cyclic redundancy codes, writing the first data and the second data to first memory devices, and writing the first parities, the first cyclic redundancy codes, the second parities, and the second cyclic redundancy codes to a second memory device and a third memory device.

Method for accessing semiconductor memory module

Memory systems include a first semiconductor memory module and a processor. The processor is configured to access the first semiconductor memory module by units of a page, and further configured to respond to an occurrence of a page fault in a specific page, which is associated with a virtual address corresponding to an access target, by adjusting a number of pages and allocating pages in the first semiconductor memory module corresponding to the adjusted number of the pages, which are associated with the virtual address.

Memory systems having semiconductor memory modules therein that support page fault processing

A memory device includes a peripheral circuit communicating with memory banks. Each of the banks includes a memory cell array including memory cells, a row decoder connected with the memory cells through word lines, bit line sense amplifiers connected with the memory cells through bit lines including first bit lines and second bit lines, and a column decoder configured to connect the bit line sense amplifiers with the peripheral circuit. The memory cell array includes a first section connected with the first bit lines and a second section connected with the second bit lines, and the first section and second section are independent of each other with regard to a row-dependent error.

Memory device and memory module including same

A memory system includes a nonvolatile memory module and a first controller configured to control the nonvolatile memory module. The nonvolatile memory module includes a volatile memory device, a nonvolatile memory device, and a second controller configured to control the volatile memory device and the nonvolatile memory device. The first controller may be configured to transmit a read request to the second controller. When, during a read operation according to the read request, normal data is not received from the nonvolatile memory device, the first controller may perform one or more retransmits of the read request to the second controller without a limitation on a number of times that the first controller performs the one or more retransmits of the read request.

Memory system including memory module, memory module, and operating method of memory module

A memory system includes a processor that includes cores and a memory controller, and a first semiconductor memory module that communicates with the memory controller. The cores receive a call to perform a first exception handling in response to detection of a first error when the memory controller reads first data from the first semiconductor memory module. A first monarchy core of the cores performs the first exception handling and the remaining cores of the cores return to remaining operations previously performed.

Memory systems and operating methods of memory systems

A semiconductor memory module may include a random access memory, a nonvolatile memory, a buffer memory, and a controller configured to execute a reading operation on the buffer memory in response to an activation of a control signal. The controller may be further configured to execute a flush operation of storing first data, which are stored in the random access memory, in the nonvolatile memory, according to a result of the reading operation.

Semiconductor memory module and memory system including the same

A memory system includes a memory device having a plurality of volatile memory modules therein, and a memory controller, which is electrically coupled to the plurality of volatile memory modules. The memory controller is configured to correct an error in a first of the plurality of volatile memory modules in response to generation of an alert signal by the first of the plurality of volatile memory modules, concurrently with an operation to refresh at least a portion of a second of the plurality of volatile memory modules upon the generation of the alert signal.

Memory module including a volatile memory device, memory system including the memory module and methods of operating a multi-module memory device

A storage module includes a dynamic random access memory (DRAM) device, a nonvolatile memory device, and a high-speed buffer memory. An method of operating the storage module includes copying target data stored in the nonvolatile memory device to the high-speed buffer memory in response to an external device entering a page fault mode, receiving a first refresh command from the external device, and, in response to the first refresh command, performing a first refresh operation associated with the DRAM device and moving the target data copied to the high-speed buffer memory to the DRAM device during a first refresh reference time.

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Seoul, South Korea

Wonjae Shin