Samsung Electronics Co., Ltd.

Seoul National University

Wonhee Cho

Wonmoon Cheon

Chanik Park

Hojun Shim

Kangho Roh

Yang-sup Lee

Jong Tae Park

Je-Hyuck Song

Moonwook Oh

Seontaek Kim

Youngjoon Choi

Jaesoo Lee

Seung-Duk Cho

Jaehoon Heo

Dongeun Shin

Jinwoo Kim

Chul-Woo Lee

Jung Hee Cheon

Jaeyong Jeong

Young-Goo Ko

Sungdong Cho

Donggi Lee

Hyuck-Sun Kwon

Hyoungyol Mun

Jinhyuck Jeong

Minsung Kang

Donggeon Yhee

Myunghyun Jo

Yeon Ju Jeong

A semiconductor device includes a semiconductor substrate including a first region and a second region, first metal lines spaced apart from each other at a first interval on the first region, second metal lines spaced apart from each other at a second interval on the second region, the second interval being less than the first interval, and a passivation layer on the semiconductor substrate and covering the first and second metal lines, the passivation layer including sidewall parts covering sidewalls of the first metal lines and the second metal lines, the sidewall parts including a porous dielectric layer, upper parts covering top surfaces of the first metal lines and the second metal lines, and an air gap defined by the sidewall parts between the second metal lines.

Semiconductor device

Each of a plurality of memory blocks of a nonvolatile memory device is divided into two or more wordline groups having different characteristics. A write command for at least two memory blocks among the plurality of memory blocks is received. During a first partial time interval included in an entire write time interval for two or more memory blocks, a data write operation is performed on a wordline group included in one memory block among the two or more memory blocks in response to a reception of an address for the one memory block. During a second other partial time interval included in the entire write time interval, a data write operation is performed on wordline groups included in the two or more memory blocks in response to a reception of an address for the two or more memory blocks.

Method of writing data in nonvolatile memory device and nonvolatile memory device performing the same

A system-on-chip includes a first intellectual property (IP) generating a plurality of request packets; and a second IP generating a plurality of response packets based on the plurality of request packets, wherein the second IP includes a plurality of processing elements processing the plurality of request packets and generating the plurality of response packets; a distributer, when the plurality of request packets are input from the first IP, determining a scheduling policy based on a packet type of the plurality of request packets and distributing the plurality of request packets to the plurality of processing elements according to the determined scheduling policy; and an aggregator, when the plurality of response packets are received from each of the plurality of processing elements, aggregating the plurality of response packets according to the determined scheduling policy.

Integrated circuit device, system-on-chip including the same, and packet processing method

An encryption method is disclosed. The encryption method includes calculating a secret key from a ring as a set closed for addition and multiplication defined between elements, generating a plurality of partial secret keys using the calculated secret key and a random matrix, and distributing the plurality of generated partial secret keys.

Apparatus for performing threshold design on secret key and method thereof

A method of operating a storage device controller which controls a storage device includes receiving a debugging data request command through a peripheral component interconnect express (PCIe) interface of the storage device controller from outside of the storage device controller, and storing debugging data in a register included in the PCIe interface.

Operation method of host system including storage device and operation method of storage device controller

A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

Memory system and method of accessing a semiconductor memory device

A storage apparatus includes a memory unit and a controller to set up a memory space of the memory unit as a user data space and a spare space according to a signal representing at least one of the user data space and spare space. An electronic apparatus controls the storage apparatus, and a method controls at least one of the storage apparatus and the electronic apparatus to control a memory space of the storage apparatus.

Defining and changing spare space and user space in a storage apparatus

One embodiment of a nonvolatile memory device includes a memory cell array including a plurality of multi-level cells, and a control unit configured to determine a characteristic of data to be stored in the memory cell array. The control unit is configured to select one of plural multi-bit programming methods based on the determination. Data is stored in the memory cell array according to the selected multi-bit programming method, and at least one of the plural multi-bit programming methods maintains least significant bit data when there is a program fail of most significant bit data.

Growing community of inventors

Anyang-si, South Korea

Wonhee Cho