Invox Technology

Wong Sau Ching

A multi-bit-per-cell memory includes a memory array having reference cells and storage cells, a read circuit, a content addressable memory, and an encoder. When data is written to the memory, a set of reference values for the write are written to the reference cells. The reference values correspond to the multi-bit digital values that can be stored in a single storage cell. For a read operation, the read circuit reads the reference values from the reference cells and stores the reference values in the content addressable memory. The read circuit then reads a data value from a storage cell associated with the reference values and applies the value read to the content addressable memory for a match operation. The output data is equal to the number or address of the entry containing the reference value that matches the data value. Since the reference and data values are written at approximately the same time and read at approximately the same time, any variations in the reference cells performance automatically tracks the performance of the storage cell. Thus, the output data value is correct even though the values that the read circuit reads from the reference and storage cells vary according to the history and current operating parameters of the memory. Write processes for the reference cells improve reference cell endurance by changing either a mapping between digital values and threshold voltages or a mapping between digital values and reference cells. A look-up table in the encoder can be re-written when the mapping between digital values and reference cells changes.

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Hillsborough, CA, United States of America

Wong Sau Ching