Skyechip Sdn Bhd

Wong Ging Yeon Mark

Chee Hak Teh

Yu Ying Ong

Tat Hin Tan

Soong Khim Chew

A device and method of clock synchronization for external memory interface. The device, and method, generating a clock output from a phase lock loop block via a sub-module clocking component; multiplexing the clock output through a global clock into different clock domains; clocking the data and an address or a command path by each clock domain; clocking the phase compensation FIFO by clock domain and clock phase alignment clock; generating the pointer for the phase compensation FIFO from central pointer generator block; and synchronizing the pointer of the adjacent intellectual property module with a parent intellectual property module.

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Bayan Lepas Pulau Pinang, Malaysia

Wong Ging Yeon Mark