Samsung Electronics Co., Ltd.

Wonchul Lee

In-Hyuk Choi

Dawoon Jung

Youngil Seo

Jungho Yun

Jae-Hoon Song

Joonhyoung Yang

Kiheum Nam

Jaehyuk Jang

Jaehyun Kim

Dongsoo Woo

Hyejin Seong

Sohyeon Bae

Hyebin Choi

Jihoon Kim

Eun Ah Kim

Min-Chul Kim

Jungwoo Song

Jin-Won Jeong

Ja Young Lee

Minwu Kim

Hosun Jung

A method of manufacturing a semiconductor device including partially etching an upper portion of a substrate to form a recess extending in a first direction parallel to an upper surface of the substrate, forming a gate structure in the recess, the gate structure including a first conductive pattern, a second conductive pattern on the first conductive pattern, and a gate mask on the second conductive pattern, partially etching an end portion of the gate structure in the first direction to form an opening, the opening extending through end portions of the gate mask and the second conductive pattern of the gate structure to expose a portion of the first conductive pattern, and a bottom of the opening being lower than a lower surface of the exposed portion of the first conductive pattern, and forming a contact plug in the opening.

Semiconductor devices

A semiconductor device includes; a semiconductor substrate including a first region and a second region, a first interlayer insulating layer on the second region, a capping layer disposed on the first interlayer insulating layer, an upper surface of the capping layer includes a first trench, conductive patterns spaced apart on the capping layer, side surfaces of the conductive patterns are aligned with inner side surfaces of the first trench, and a peripheral separation pattern disposed in the first trench to cover the side surfaces of the conductive patterns. The peripheral separation pattern has a first thickness on the side surfaces of the conductive patterns and a second thickness greater than or equal to the first thickness on a lower surface.

Semiconductor device and method of fabricating same

A semiconductor memory device includes a substrate including memory cell, peripheral, and intermediate regions; a device isolation pattern; a partitioning pattern; bit lines extending in a first direction to a boundary between the intermediate and peripheral regions; storage node contacts on the memory cell region and filling a lower portion of a space between bit lines; landing pads on the storage node contacts; dummy storage node contacts on the intermediate region and filling a lower portion of a space between bit lines; dummy landing pads on the dummy storage node contacts; and a dam structure on the intermediate region, extending in the first direction, and having a bar shape, wherein the dummy landing pads are spaced apart from an edge of the dam structure in a second direction, and the dummy storage node contacts are in contact with the partitioning pattern.

Semiconductor memory device

A semiconductor memory device includes a substrate having a memory cell region where a plurality of active regions are defined; a word line having a stack structure of a lower word line layer and an upper word line layer and extending over the plurality of active regions in a first horizontal direction, and a buried insulation layer on the word line; a bit line structure arranged on the plurality of active regions, extending in a second horizontal direction perpendicular to the first horizontal direction, and having a bit line; and a word line contact plug electrically connected to the lower word line layer by penetrating the buried insulation layer and the upper word line layer and having a plug extension in an upper portion of the word line contact plug, the plug extension having a greater horizontal width than a lower portion of the word line contact plug.

Semiconductor memory devices having contact plugs

A semiconductor device includes a gate structure and a contact plug. The gate structure extends in a first direction parallel to the substrate, and includes a first conductive pattern, a second conductive pattern and a gate mask sequentially stacked. The contact plug contacts an end portion in the first direction of the gate structure, and includes a first extension portion extending in a vertical direction and contacting sidewalls of the gate mask and the second conductive pattern, a second extension portion under and contacting the first extension portion and a sidewall of the first conductive pattern, and a protrusion portion under and contacting the second extension portion. A bottom of the protrusion portion does not contact the first conductive pattern. A first slope of a sidewall of the first extension portion is greater than a second slope of a sidewall of the second extension portion.

A semiconductor device comprises a plurality of pillars on a semiconductor substrate, and a support pattern in contact with at least one side surface of each of the pillars. The support pattern connects the pillars with one another. The support pattern includes a plurality of support holes that expose side surfaces of the pillars. The support holes includes a first support hole and a second support hole that are spaced apart from each other. The pillars have circular cross-sections. A ribbon-like hexagon is obtained in a plan view when connecting an inner sidewall of the first support hole with central points of the cross-sections of the pillars exposed through the first support hole.

Semiconductor devices including support patterns

A semiconductor device includes a plurality of pillar structures on a semiconductor substrate, and a support pattern in contact with at least a part of each of the pillar structures, the support pattern connecting the pillar structures with one another, wherein the support pattern includes support holes exposing side surfaces of the pillar structures, the support holes including at least a first support hole and a second support hole that are spaced apart from each other, the first and second support holes having different shapes from each other.

A semiconductor device includes a substrate including a cell region and peripheral region and bottom electrodes on the substrate. The bottom electrodes are arranged in a first row and a second row each extending in a first direction. The first row and the second row are adjacent to each other in a second direction perpendicular to the first direction. The bottom electrodes in the first row include an outermost bottom electrode and a next outermost bottom electrode that are separated by a first distance in the first direction. The bottom electrodes in the second row include an outermost bottom electrode and a next outermost bottom electrode that are separated by a second distance in the first direction. The outermost bottom electrode in the first row is on the peripheral region of the substrate. The outermost bottom electrode in the second row is on the cell region of the substrate.

A memory controller controlling a nonvolatile memory device having a plurality of memory blocks as a data storage space includes an error detection and correction circuit and a reclaim control unit. The error detection and correction circuit receives data from a memory block and calculates a comparison result by comparing a bit error rate of the received data and a predetermined value. The reclaim control unit determines whether or not to perform a read reclaim operation depending on the comparison result and a read voltage used to read the data. The read reclaim operation copies the data to a memory block different from a memory block having stored the data.

Memory controller, method of operating the same and memory system including the same

Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include storage node pads disposed adjacent to each other between word lines but spaced apart from each other by an isolation pattern. Accordingly, it is possible to prevent a bridge problem from being caused by a mask misalignment. This enables to improve reliability of the semiconductor device.

Semiconductor device and method of fabricating the same

A memory system comprises a nonvolatile memory comprising a memory block having multiple pages, and a controller configured to control the nonvolatile memory to store data in the memory block according to a command and logical address received from an external source. The controller is configured to determine whether the logical address is currently mapped to a bad page of the memory block by referring to a bad page map, and as a consequence of determining that the logical address corresponds to the bad page, remaps the logical address to a different page and stores dummy data in the bad page.

Growing community of inventors

Seongnam-si, South Korea

Wonchul Lee