Industrial Technology Research Institute

Won-Yih Lin

Ming-Fen Lin

Wen-Zen Shen

Ming-Tsan Kao

Ching-Chin Huang

Yea-Yun Yang

Hong-Chich Chou

Ming-Mao Chiang

Jerng-Cherng Fan

Chong-Ching Chen

Chi-Chih Lee

An apparatus and method for controlling an asynchronous dual port FIFO memory is provided. The asynchronous FIFO may operate at frequencies satisfying 0.5f,<f,<f,or 0.5f,<f,<f,, where f,is the write frequency if f,is the read frequency, or vice versa. A FIFO in accordance with the present invention comprises a dual port random access memory, a read pointer, a write pointer, a synchronization circuit and a status indicator. In the FIFO design, the read pointer indicating the read address is a simple sequential counter, and the write pointer indicating the write address is a Gray code counter. Gray code to sequential count converters are used to convert the Gray codes to sequential counts. The synchronization circuit synchronizes the write pointer and the read pointer using a read clock. A status indicator with simple circuits is provided to indicate if the FIFO is almost full or empty.

Apparatus and method for asynchronous dual port FIFO

An interrupt processing method and apparatus particularly well-suited for use in an interrupt controller of a multiprocessor system or device. Each of the interrupt requests has at least one destination processor associated therewith for servicing the interrupt request. An interrupt controller in accordance with the present invention applies latched interrupt requests to a priority compare tree which serves to prioritize received interrupt requests. A number of higher priority requests, including the highest priority request, are supplied to a destination selection circuit which includes an interrupt dispatcher which determines a processor to which the first priority interrupt request will be dispatched. Similar determinations are made for the remaining identified interrupt requests, but with the corresponding destination register contents masked to prevent processors already selected to receive a higher priority interrupt from being considered for a lower priority interrupt. The destination selection circuit attempts to determine a unique destination processor for each of the highest priority interrupt requests, such that these multiple interrupt requests can therefore be dispatched to different processors simultaneously. One or more of the interrupt requests may be 'blocked' during a particular time period because all destination processors which could service the blocked requests are already processing other interrupts, performing higher priority tasks or are otherwise unavailable. These blocked interrupt requests are identified and the corresponding destination registers are masked such that the remaining non-blocked interrupt requests can be delivered to an available destination processor.

Method and apparatus for selecting a nonblocked interrupt request

A modified three-pixel antialiasing method wherein the closest pixel from a displayed line has a constant display intensity includes the steps of locating a first pixel having a shortest distance along an axis of the pixel matrix array from the line, determining the shortest distance, calculating pixel intensity for the first pixel by multiplying a maximum intensity of the first pixel with a constant value, locating a second pixel having a second shortest distance along the axis from the line, locating a third pixel having a third shortest distance along the axis from the line, calculating pixel intensity for the second pixel, and calculating pixel intensity for the third pixel.

Method for antialiasing

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Taichung, Taiwan

Won-Yih Lin