Yonsei University

Samsung Electronics Co., Ltd.

Skhynix Inc.

Won Woo Ro

Hongju Kal

Gun Ko

Jiwon Lee

Wonseb Jeong

Hyunwuk Lee

Jae-Ho Kim

Jin-Won Kim

Sun-Mi Kim

Seung Hun Kim

Seokmin Lee

Keunsoo Kim

Ipoom Jeong

Sung Ho Kim

Youngju Lee

Chan-yul Kim

Sun-il Lee

Minwoo Kim

Byungchul Kim

Ho Young Kim

Seongil O

Minsik Kim

Won Hyun Jeon

Jonghyun Lee

Seungku Han

Ho-jun Shim

Kyungah Kim

ChangMin Lee

Min Seong Kim

Sung Jae Lee

Sung Tak Cho

Jeong-ho Lee

Jeonghoon Choi

Joon Kee Chang

William Jinho Song

Jun Hyun Park

Yong Tag Song

Hyun Jae Oh

Hyoseong Choi

Sung Ji Choi

Chanyoung Yoo

Seunghyun Jin

Won Seob Jeong

Joo Hyeong Yoon

Won Seb Jeong

Keun Soo Kim

Hyunjin Chung

Sang Peel Lee

Myung Kuk Yoon

Yun Ho Oh

Keun Baek Park

Doo Hwan Oh

Young Jae Cho

Kijoon Chang

Karam Park

Myungkuk Yoon

A memory management unit includes a TLB configured to cache PTEs including a mapping between a virtual and a physical frame number, and to convert a virtual address into a physical address using the cached PTEs. A page table walk request queue is configured to queue page requests corresponding to a virtual page number when a TLB miss is occurred, and one or more PTWs are configured to acquire a PTE from the main memory, and to convert the virtual page numbers into physical frame numbers using the PTE. A PTW is configured to select associated page table walk requests having the same base address of corresponding virtual page numbers, to consecutively provide cache line requests for acquiring PTEs corresponding to the associated page table walk requests, to acquire the PTEs corresponding to the associated PTE requests, and to provide the acquired PTEs to the TLB.

Memory management unit and method of walking page table

Disclosed is a method of operating a swap memory device configured to communicate with a host device and a main memory device. The method includes receiving, from the host device, a request corresponding to target data, determining, by the swap memory device, a first address of the target data and a second address of a target data block that includes the target data, based on the request, providing, by the swap memory device, the target data to the host device based on the first address, and providing, by the swap memory device, the target data block to the main memory device based on the second address.

Swap memory device providing data and data block, method of operating the same, and method of operating electronic device including the same

An apparatus and method with register sharing are provided. In one general aspect, a method of operating a processing apparatus includes determining whether there is shared data that is used by each of threads in a plurality of threads sharing a shared memory, based on an instruction that has been decoded, based on determining whether there is shared data that is used by each of the threads in the plurality of threads, determining whether an address of the shared data corresponding to each of the threads in the plurality of threads is stored in an address-to-register mapping table, based on a result of either the determining whether the address is stored in the address-to-register mapping table, mapping the address of the shared data to a shared register corresponding to the shared data, and loading the shared data based on the shared register.

Apparatus and method with register sharing

A data processing system and method for accessing a heterogeneous memory system including a processing unit are provided. The heterogeneous memory system includes a memory module and high bandwidth memory (HBM) including a processing-in-memory (PIM) circuit combined with a memory controller. The memory controller is configured to detect a data array required for an arithmetic operation from a memory module or the HBM by using a border index value when the arithmetic operation is performed by the PIM circuit of the HBM and generate a memory module command set and an HBM command set using physical address spaces respectively designated in the memory module and the HBM.

Data processing system and method for accessing heterogeneous memory system including processing unit

Disclosed is a memory system using a heterogeneous data format, which provides a personalized recommendation algorithm function to an internet service user based on a plurality of items, which includes a user preference analyzer for each item that calculates a user preference value corresponding to each item of a analysis target service; and a memory that stores data related to the each item in a first data format or stores data related to the each item in a second data format with required bits less than the first data format, based on the user preference value of the each item.

Memory system using heterogeneous data format and method of controlling the same

Disclosed is an accelerator and a method of operating the accelerator including determining whether any group shares weights of a first group from among groups, determining a presence of an idle processing element (PE) array, in response to no group sharing the weights of the first group, and selecting a second group having a memory time overlapping a computation time of the first group from among the groups, in response to the idle PE array being present.

Accelerator for processing inference tasks in parallel and operating method thereof

A controller is provided. The controller creates a page table including page table entries including mapping information for translating a virtual address to a physical address. Each of the page table entries includes: a virtual page number, a physical frame number, valid information, and size information. The virtual page number is included in a virtual address, the physical frame number is included in a physical address, the valid information includes a first predetermined number of bits, and the size information includes a second predetermined number of bits. The first predetermined number of bits represents an address translation range in a page table entry or a number of page table entries to be grouped, and the size information represents a size indicated by each bit of the first predetermined number of bits.

Controller, computing system including the same, and method of creating and searching page table entry for the same

A storage system includes a storage device having a nonvolatile memory with a first and a second physical address and a host configured to insert a first journal logical address and a first target logical address into a journal mapping table. The storage device includes a flash mapping table storing the first journal logical address mapped to the first physical address, and the first target logical address mapped to the second physical address; a circuit configured to write the first journal data to an area of the nonvolatile memory to the first physical address corresponding to the first journal logical address according to the first mapping state, based on the journaling command; and to change the first mapping state of the flash mapping table to a second mapping state in which the first target logical address is remapped to the first physical address, based on the checkpointing command.

Storage device, storage system, and method of operating the storage system

Provided are a GPU and a method of managing a memory address thereby. TLBs are configured using an SRAM and an STT-MRAM so that a storage capacity is significantly improved compared to a case where a TLB is configured using an SRAM. Accordingly, the page hit rate of a TLB can be increased, thereby improving the throughput of a device. Furthermore, after a PTE is first written in the SRAM, a PTE having high frequency of use is selected and moved to the STT-MRAM. Accordingly, an increase in TLB update time which may occur due to the use of the STT-MRAM having a low write speed can be prevented. Furthermore, a read time and read energy consumption can be reduced.

Memory management device capable of managing memory address translation table using heterogeneous memories and method of managing memory address thereby

The embodiments provide a register file device which increases energy efficiency using a spin transfer torque-random access memory for a register file used to compute a general purpose graphic processing device, and hierarchically uses a register cache and a buffer together with the spin transfer torque-random access memory, to minimize leakage current, reduce a write operation power, and solve the write delay.

Hierarchical register file device based on spin transfer torque-random access memory

Disclosed is a 5G or pre-5G communication system for supporting a data transmission rate higher than that of a 4G communication system such as LTE. The present invention relates to a method by which a simulator analyzes a radio wave environment in a wireless communication system, and the method of the present invention comprises the steps of: allowing a simulator to receive geographic information and position information by which a transmitter and a receiver can be positioned in the geographic information; generating, by the transmitter of the simulator arranged at a random position in accordance with the position information, radio waves for at least one direction of a sphere having a fixed radius; grouping into at least one group on the basis of a traveling route of the generated radio waves; setting each group as an operation unit (Warp/Wavefront) for a graphics processing unit (GPU); and analyzing a radio wave environment by using the GPU in which the operation unit is set.

Method and device for allowing simulator to analyze radio wave environment in wireless communication system

A memory system includes a memory device including a first area being refreshed according to a first refresh period and a second area begin refreshed according to a second refresh period longer than the first refresh period. The memory system also includes a memory controller configured to generate a write command and a write data corresponding to a first write request and a first data.

Memory device including a plurality of area having different refresh periods, memory controller controlling the same and memory system including the same

Provided is an image encoding method including extracting feature points from a picture; generating at least two clusters by performing feature point clustering on the extracted feature points; determining at least two split sections in the picture, the at least two split sections respectively corresponding to the at least two clusters; parallel-encoding the at least two split sections; and generating a bitstream including information about the at least two split sections. A size and a shape of each of the at least two split sections may be individually determined.

Method and apparatus for encoding image by using atypical split, and method and apparatus for decoding image by using atypical split

Provided is a removable storage system including: a data storage device configured to store a plurality of files including a first file and a second file; a host interface configured to receive, from a host, a pattern matching request including pattern information and file information regarding the plurality of files, and transmit, to the host, a result of pattern matching regarding the plurality of files; and a pattern matching accelerator configured to perform the pattern matching in response to the pattern matching request, wherein the pattern matching accelerator includes a scan engine configured to scan data based on a pattern, and a scheduler configured to control the scan engine to stop scanning the first file and start scanning the second file.

Storage system and operating method thereof

Growing community of inventors

Seoul, South Korea

Won Woo Ro