Skhynix Inc.

Won Tae Koo

Jae Hyun Han

Jae Gil Lee

Woo Cheol Lee

Se Ho Lee

Dong Ik Suh

Mir Im

An electronic device according to an embodiment of the present disclosure includes a substrate, a base electrode layer disposed over the substrate, first and second operating electrode layers disposed over the base electrode layer to be spaced apart from each other, a channel layer disposed between the first operating electrode layer and the second operating electrode layer over the base electrode layer, a proton conductive layer disposed over the first and second electrode layers and the channel layer, a hydrogen source layer disposed over the proton conductive layer, and a control electrode layer disposed over the hydrogen source layer.

Electronic device having resistance change property

A semiconductor device according to an embodiment of the present disclosure includes a first electrode, a first resistance change layer disposed on the first electrode, a conduction control layer disposed on the first resistance change layer, a second resistance change layer disposed on the conduction control layer, and a second electrode disposed on the second resistance change layer. The conduction control layer includes a metal-organic framework layer and metal particles embedded in the metal-organic framework layer.

Semiconductor device including resistance change layer and metal particle-embedded metal-organic framework layer and method of manufacturing the same

A semiconductor device according to an embodiment of the present disclosure includes a substrate, a first epitaxial electrode layer disposed on the substrate, a ferroelectric epitaxial layer disposed on the first epitaxial electrode layer, a dielectric epitaxial layer disposed on the ferroelectric epitaxial layer, and a second epitaxial electrode layer disposed on the dielectric epitaxial layer. The ferroelectric epitaxial layer implements a negative capacitance. Each of the first and second epitaxial electrode layers includes conductive pyrochlore oxide. The ferroelectric epitaxial layer and the dielectric epitaxial layer are electrically connected in series is non-ferroelectric. A dielectric structure comprising the ferroelectric epitaxial layer and the dielectric epitaxial layer is non-ferroelectric.

Semiconductor device including epitaxial electrode layer and dielectric epitaxial structure and method of manufacturing the same

A semiconductor device includes a first conductive layer including a first metal, a second conductive layer electrically connected to the first conductive layer and including a second metal, and an interconnection structure common to a connection portion of the first and second conductive layers. The interconnection structure may include a seed layer on the first conductive layer that includes graphene, and a metal migration barrier layer on the seed layer that includes MXene.

Semiconductor device including interconnection structure including MXene and method of manufacturing the same

A semiconductor device includes a substrate, a ferroelectric layer disposed on the substrate, a gate insulation layer disposed on the ferroelectric layer, metal particles disposed in the gate insulation layer, and a gate electrode layer disposed on the gate insulation layer.

Semiconductor device including ferroelectric layer and insulation layer with metal particles and methods of manufacturing the same

An electronic device includes a base element, a source electrode layer and a drain electrode layer disposed to be spaced apart from each other on the base element, a channel layer disposed between the source electrode layer and the drain electrode layer on the base element that accommodates metal ions, a metal ion conduction layer disposed on the channel layer, and a gate electrode layer disposed on the metal ion conduction layer. The channel layer includes a plurality of unit films and channel spaces between the plurality of unit films. The plurality of unit films are arranged to be parallel to a direction substantially perpendicular to a surface of the base element.

Electronic device including channel layer including variable resistance and method of manufacturing the same

An electronic device includes a substrate, a source electrode layer and a drain electrode layer that are disposed to be spaced apart from each other over the substrate, a channel layer that is capable of receiving hydrogen, disposed between the source electrode layer and the drain electrode layer over the substrate, a proton conductive layer disposed on the channel layer, a hydrogen source layer disposed on the proton conductive layer, and a gate electrode layer disposed on the hydrogen source layer.

Electronic device including proton conductive layer and resistance change channel layer capable of receiving hydrogen

Disclosed semiconductor devices include a substrate, a device pattern structure disposed over the substrate, and a heat insulating layer disposed on the device pattern structure. The device pattern structure includes metal-organic frameworks.

Semiconductor device including heat insulating layer and method of manufacturing the same

A semiconductor device according to an embodiment of the present disclosure includes a substrate, a gate structure disposed over the substrate, a dielectric structure disposed to contact a sidewall surface of the gate structure over the substrate, and a channel layer disposed on a sidewall surface of the dielectric structure over the substrate. The gate structure includes a gate electrode layer and an interlayer insulation structure which are alternately stacked. The interlayer insulation structure includes a metal-organic framework layer.

Semiconductor device including interlayer insulation structure including metal-organic framework

A method of manufacturing a semiconductor device comprises: providing a substrate; forming a ferroelectric layer on the substrate; stacking two-dimensional conductive metal-organic frameworks that include cavities on the ferroelectric layer to form a metal-organic framework layer, the cavities of the conductive metal-organic frameworks being disposed to overlap with each other in a thickness direction of the metal-organic framework layer; disposing metal particles within the overlapping cavities to form a charge trap layer; forming a gate insulation layer on the charge trap layer; and forming a gate electrode layer on the gate insulation layer.

Semiconductor device including ferroelectric layer and metal particles embedded in metal-organic framework layer

In a method of treating a target film, a plurality of pattern structures with sidewall surfaces facing each other are provided. A target film is formed on the sidewalls of the plurality of pattern structures. A plurality of nanoparticles are distributed on the target thin film. The target thin film is thermally treated by irradiating laser light from upper sides of the plurality of pattern structures to the target thin film. The irradiated laser light is scattered from the plurality of nanoparticles.

Method of treating target film and method of manufacturing semiconductor device

A semiconductor device includes a substrate and a gate structure disposed over the substrate. The gate structure includes gate electrode layers and interlayer insulation structures that are alternately stacked with each other. The semiconductor device includes a dielectric structure disposed over the substrate to contact a sidewall surface of the gate structure, and a channel layer disposed on a sidewall surface of the dielectric structure over the substrate. Each of the interlayer insulation structure includes an insulation layer and a metal-organic framework layer that are disposed on the same plane.

Semiconductor device with interlayer insulation structure including metal-organic framework layer and method of manufacturing the same

A semiconductor memory device includes a tunnel insulating layer, a data storage layer, and a blocking insulating layer that are sequentially disposed. The tunnel insulating layer includes Metal Organic Frameworks (MOF) having a lower dielectric constant than a dielectric constant of the blocking insulating layer.

Semiconductor memory device

A semiconductor device includes a substrate, a ferroelectric layer disposed on the substrate in a vertical direction, a charge trap layer disposed on the ferroelectric layer, a gate insulation layer disposed on the charge trap layer, and a gate electrode layer disposed on the gate insulation layer. The charge trap layer includes a metal-organic framework layer and metal particles embedded in the metal-organic framework layer.

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Icheon-si, South Korea

Won Tae Koo