Skhynix Inc.

Hynix Semiconductor Inc.

Korea University Research and Business Foundation

Won Sun Park

Jae Young Lee

Tae Ho Jeon

Kyung Ho Lee

Chang Yeon Kim

Yong Soon Park

Han Bin Lee

Ju Hyeon Lee

Sang Hyun Song

Youngin You

Dahee Choi

Mi Ock Chi

Geonu Kim

Junhyoung Oh

So Jin Jeong

A semiconductor system includes a first semiconductor apparatus and a second semiconductor apparatus. The first semiconductor apparatus provides the second semiconductor apparatus with a chip enable signal and a command address signal set, and the second semiconductor apparatus performs an internal operation based on the chip enable signal and the command address signal set. The first semiconductor apparatus provides the second semiconductor apparatus with a selection chip enable command, and the second semiconductor apparatus transmits data to the first semiconductor apparatus or receives the data from the first memory device after receiving the selection chip enable command.

Semiconductor apparatus and semiconductor system having independent data input/output period, and operating method of the semiconductor system

A semiconductor system includes a first semiconductor apparatus and a second semiconductor apparatus. The first semiconductor apparatus transmits a command signal during a command cycle and transmits an address signal during an address cycle. The first semiconductor apparatus transmits a selection signal during a LUN selection cycle before the command cycle. The second semiconductor apparatus performs a data input/output operation based on the selection signal, the command signal, and the address signal.

Semiconductor apparatus and semiconductor system having lun selection cycle, and operating method of semiconductor system

A semiconductor system includes a first semiconductor apparatus and a second semiconductor apparatus. The first semiconductor apparatus transmits an address signal during an address cycle after transmitting a command signal during a command cycle. The first semiconductor apparatus transmits a selection signal during a logical unit number selection cycle before the command cycle. The second semiconductor apparatus performs a data input and output operation based on the selection signal, the command signal, and the address signal.

Semiconductor apparatus and semiconductor system having LUN selection cycle, and operating method of semiconductor system

A data storage device may include a memory device divided into a plurality of logical units, and a controller configured to generate a first read command sequence and a second read command sequence for a first logical unit and a second logical unit, respectively, among the plurality of logical units, in response to an external command and configured to continuously output the first and second read command sequences to the memory device.

Data storage device and read operation control method thereof

A semiconductor memory device includes a storage, a buffer, and a control logic. The storage stores a first algorithm data. The buffer stores a second algorithm data that is at least partially different from the first algorithm data. The control logic is configured to selectively receive the first algorithm data and the second algorithm data.

Semiconductor memory device and method of operating the same

Disclosed is an apparatus for managing a risk of a malware behavior in a mobile operating system, which includes: a deducing unit configured to deduce characteristics of a malware from results of a static analysis on mobile malware data and a dynamic analysis thereon under a virtual environment by using a blacklist including an indicator of compromise (IOC) utilized in an existing mobile malware.

Apparatus and method for managing risk of malware behavior in mobile operating system and recording medium for perform the method

The memory device includes: an independent circuit configured to output an independent signal; a memory cell array formed on a top of the independent circuit, the memory cell array including a plurality of memory cells in which data is stored; a revision circuit formed on a top of the memory cell array, the revision circuit storing modified ROM data different from the independent signal, the revision circuit outputting a ROM control signal and the modified ROM data in response to a select signal when an error occurs in the independent signal in a test operation of the independent circuit formed under the memory cell array; and a selection circuit configured to output the independent signal or the modified ROM data in response to the ROM control signal.

Memory device and memory system having the same

Provided herein is a semiconductor memory device. The semiconductor memory device includes: a memory cell array including a plurality of memory blocks; a voltage generation circuit configured to generate a plurality of operating voltages; a decoder circuit configured to transmit the plurality of operating voltages to the memory cell array in response to a serial data signal that is sequentially inputted; and a control logic configured to generate the data signal, internal address signals and an internal clock signal in response to a command.

Semiconductor memory device

In one aspect of the present disclosure, there is provided a memory system comprising a memory device configured to temporarily store data therein, the data being loaded thereon for programming a selected page among multiple pages, the memory device further configured to program the selected page using the data; and a controller configured to send the data to the memory device, wherein the controller is further configured to control the memory device such that, in a failure event of the program for the selected page, the memory device re-programs another page using the data temporarily stored therein without receipt of further data from the controller.

Memory system with reduced program time and method of operating the same

A memory system in accordance with an embodiment may include a memory chip and a controller. The memory chip may store data in a plurality of logical pages by performing a sensing operation on a selected page in response to commands and performing an output operation of the data. The controller may transmit the commands to the memory chip so that a part of the sensing operation and a part of the output operation are simultaneously performed.

Memory system and method of operating the same

The semiconductor memory device includes a memory cell array including guarantee blocks, normal blocks, and redundancy blocks. A bad block address indicates which block from the guarantee blocks and the normal blocks is defective, and an indication information indicates whether the bad block address belongs to the guarantee blocks or to the normal blocks. A request block address is supplied together with associated block type information. The block type information indicates whether the request block address belongs to the guarantee blocks or to the normal blocks. A match signal is enabled when the block type information matches the indication information, and the request block address matches the bad block address. The enablement of the match signal allows the defective block to be replaced with one block from the redundancy blocks.

A memory system including a plurality of memory chips is provided. The memory system includes a first memory chip and a second memory chip that share a data bus and become active by a chip enable signal, and a controller transmitting multi chip select commands to the first and second memory chips. The first memory chip, in response to the first multichip select command, receives a first operation request transmitted by the controller through the data base, and the second memory chip, in response to the second multichip select command, receives a second operation request transmitted by the controller through the data bus before the first memory chip operates according to the first operation request.

Semiconductor memory device, memory system and method of operating the same

A semiconductor device includes a first operation circuit configured to generate addition data by adding a column address and a page address and output a remainder obtained by dividing the addition data by a set value as seed data, a mask data output circuit configured to output mask data corresponding to the respective seed data, and a second operation circuit configured to generate random data by performing a logic operation on the mask data and program data corresponding to the column and page addresses.

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Seoul, South Korea

Won Sun Park