Samsung Electronics Co., Ltd.

Won-suk Yang

Ki-nam Kim

Hong-sik Jeong

Ki-Nam Kim

Yoo-Sang Hwang

Jae-young Lee

Chang-hyun Cho

Sang-Ho Song

Chang-Hyun Kim

Kyung-Ho Kim

Moo-Sung Kim

Seung-Hyun Park

Sang-Hun Seo

Han-Sin Lee

Chang-gyu Hwang

Min-uk Hwang

A semiconductor device and manufacturing method thereof include a semiconductor substrate, an interlevel dielectric (ILD) layer formed on the semiconductor substrate, a first contact stud formed in the ILD layer, having a width of an entrance portion adjacent to the surface of the ILD layer larger than the width of a contacting portion adjacent to the semiconductor substrate, and a second contact stud spaced apart from the first contact stud and formed in the ILD layer. The semiconductor device further includes a landing pad formed on the ILD layer to contact the surface of the second contact stud, having a width larger than that of the second contact stud. The second contact stud has a width of a contacting portion that is the same as that of an entrance portion. Also, at least one spacer comprising an etch stopper material is formed on the sidewalls of the landing pad and the etch stopper is formed on the landing pad. The entrance portion of the first contact stud has a width about 30-60% larger than that of the contacting portion.

Semiconductor device having multilayer interconnection structure and manufacturing method thereof

A CMOS semiconductor device and a method of manufacturing the same in which the gate induced drain leakage (GIDL) effect is reduced. In the semiconductor device of this invention, high concentration source/drain regions of a PMOS transistor are formed away from the gate pattern sidewall spacers. This is accomplished by using as an implant mask a dielectric film formed on an entire surface of a semiconductor substrate, where the semiconductor substrate includes a PMOS transistor region in an n-well, a low concentration source/drain regions of a PMOS transistor formed by using a gate pattern as an implant mask, the PMOS transistor gate pattern sidewall spacers, and an NMOS transistor region in a p-well with the NMOS transistor having both a low concentration and a high concentration source/drain regions.

Method of manufacturing the semiconductor device intended to prevent a leakage current from occuring due to a gate induced drain leakage effect

A semiconductor device and manufacturing method thereof include a semiconductor substrate, an interlevel dielectric (ILD) layer formed on the semiconductor substrate, a first contact stud formed in the ILD layer, having a line width of an entrance portion adjacent to the surface of the ILD layer larger than the line width of a contacting portion adjacent to the semiconductor substrate, and a second contact stud spaced apart from the first contact stud and formed in the ILD layer. The semiconductor device further includes a landing pad formed on the ILD layer to contact the surface of the second contact stud, having a line width larger than that of the second contact stud. The second contact stud has a line width of a contacting portion that is the same as that of an entrance portion. Also, at least one spacer comprising an etch stopper material is formed on the sidewalls of the landing pad and the etch stopper is formed on the landing pad. The entrance portion of the first contact stud has a line width about 30-60% larger than that of the contacting portion.

A method for arranging a power supply line in a semiconductor device including a plurality of memory cell array blocks and a semiconductor device are provided in order to supply stable operating voltages, such as a power supply voltage and a ground voltage, to a sense amplifier allocated to each of the plurality of memory cell array blocks. The method includes the steps of arranging a plurality of first interconnections that extend in one direction and are spaced apart from one another on a semiconductor substrate on which the plurality of memory cell array blocks are formed, forming a first insulating layer on the plurality of first interconnections, arranging a plurality of power reinforcing lines that extends in one direction and are spaced apart from one another on the plurality of first interconnections on the first insulating layer, forming a second insulating layer on the plurality of power reinforcing lines, and arranging a plurality of second interconnections that intersect the plurality of first interconnections and the plurality of power reinforcing lines on the second insulating layer. The plurality of second interconnections include a first group and a second group, and the second interconnections in the second group are electrically connected to the plurality of power reinforcing lines on the plurality of memory cell array blocks via contact plugs formed in the second insulating layer.

Method for arranging wiring line including power reinforcing line and semiconductor device having power reinforcing line

An etch-stop layer is selectively provided between layers of a multiple-layered circuit in a selective manner so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying stud so as to serve as an alignment target during formation of an overlying stud formed in an upper layer. In this manner multiple-layered circuits, for example memory devices, can be fabricated in relatively dense configurations.

Bit line landing pad and borderless contact on bit line stud with localized etch stop layer formed in void region, and manufacturing method thereof

Bit line pad and borderless contact on bit line stud with localized etch stop layer formed in an undermined region

Bit line landing pad and borderless contact on bit line stud with localized etch stop layer and manufacturing method thereof

A semiconductor memory device from which a floating body effect is eliminated and which has enhanced immunity to external noise, and a method of fabricating the same are provided. The memory device includes a semiconductor substrate. A plurality of bit lines are buried in the semiconductor substrate such that the surfaces of the bit lines are adjacent to the surface of the semiconductor substrate. The bit lines are arranged in parallel with one another. A plurality of word lines are formed on the semiconductor substrate so that the word lines cross and are isolated from the bit lines. A plurality of vertical access transistors are formed at individual memory cells where the bit lines and the word lines intersect. Each vertical access transistor includes a first source/drain region, a body region including a vertical channel region and a second source/drain region which are formed sequentially on the bit line. The vertical access transistor contacts a gate insulation layer formed on a portion of one side of the sidewalls of the word line. Body regions including the channel regions of the access transistors are connected to one another to be a single integrated region.

Semiconductor memory device for eliminating floating body effect and method of fabricating the same

An etch-stop layer is selectively provided between layers of a multiple-layered circuit in a selective manner so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying stud so as to serve as an alignment target during formation of an overlying stud formed in an upper layer. In this manner multiple-layered circuits, for example memory devices, can be fabricated in relatively dense

An etch-stop layer is selectively provided between layers of a multiple-layered circuit so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying stud so as to serve as an alignment target during formation of an overlying stud formed in an upper layer to be coupled to the underlying stud. In this manner multiple-layered circuits, for example memory devices, can be fabricated in relatively dense configurations.

Bit line landing pad and borderless contact on bit line stud with etch stop layer and manufacturing method thereof

An improved isolation method in a semiconductor device of selective polysilicon oxidation (SEPOX) which can create a field oxide layer having a size below the optical resolution and good isolation characteristics. A buffer layer comprised of polysilicon or amorphous silicon is formed on a semiconductor substrate, and then an anti-oxidative pattern with an opening which defines an isolation region exposing a portion of the buffer layer is formed. Then a portion of the exposed buffer layer is isotropically etched in order to form an undercut portion in the lower portion around the opening. Then an anti-oxidative spacer filling the undercut portion is formed on the sidewall of the opening. Thereafter, a field oxide layer is formed by partially oxidizing the portion of the buffer layer exposed by the opening and the semiconductor substrate exposed in the opening. The size of bird's beak is decreased, thereby forming a field oxide layer with good isolation characteristics and small size.

Isolation method for semiconductor device

A method for forming a fine pattern of a semiconductor device, in which a first-to-be-patterned layer is formed on a semiconductor substrate, a photoresist film is coated on the first-to-be-patterned layer, and the photoresist film is patterned and cured to obtain a thermally stable photoresist film pattern. Thereafter, a second material layer is formed on the entire surface of the semiconductor substrate on which the photoresist film pattern is formed, by a low temperature plasma method, and the second material layer is anisotropically etched to thereby form a spacer made of the second material layer on the sidewalls of the photoresist film pattern. A first pattern is formed by anisotropically etching the first-to-be-patterned layer, using the spacer and the photoresist film pattern as an etching mask. The spacer and the photoresist film pattern are then removed. Using the first pattern thus obtained, a fine pattern which is the inverse of the first pattern can be formed. The separation interval between the individual elements can be reduced so as to be less than or equal to the minimum design rule, and a fine pattern below optical resolution can be attained.

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Yongin, South Korea

Won-suk Yang