Samsung Electronics Co., Ltd.

Chabio & Diostech Co., Ltd

Won-Suk Yang

Ki-nam Kim

Ki-Nam Kim

Hong-Sik Jeong

Soo-ho Shin

Chang-hyun Cho

Chan-Seok Yang

Sang-Hoo Song

Sung-Jin Park

Jin-Woo Lee

Chang-Hyun Kim

Tae-Young Chung

Kyung-Ho Kim

Jae-Kyu Lee

Ho-Chul Shin

Jai-Hoon Sim

Byung-Soo Lim

Won-Sang Kwon

Eun-Cheol Lee

Kyoung Tae Jung

Jin-Kyu Park

Disclosed is a quickly soluble oral film dosage for masking a nasty taste, in particular, a quickly soluble oral film dosage comprising a stevioside based sweetener and a high potency sweetener in a ratio by weight (w/w) of 1:3 to 3:1, which may efficiently mask a bitter or nasty taste of a medicine and may be quickly dissolved in a mouth without water, thereby improving an aftertaste thereof thus enhancing dosage acceptability of a patient.

Quickly soluble oral film dosage containing steviosides as a unpleasant taste masking agent

An image management method and system are disclosed which can increase user convenience by reducing a display time of thumbnails in a DLNA system. The DLNA system includes a digital media server for generating a thumbnail group image using thumbnails corresponding to at least one original image file and transmitting the thumbnail group image, and a digital media player for receiving the thumbnail group image from the digital media server and requesting the digital media server to transmit an original image file corresponding to a selected thumbnail among thumbnails included the thumbnail group image.

Image management method and system using thumbnail in DLNA system

A music linked photocasting service system and method are provided. The music linked photocasting service method includes reproducing music at the request of a user, analyzing a mood of the reproduced music at prescribed times, until music reproduction is completed, searching photographs suitable for a analyzed mood of the music, and displaying the searched photographs.

Music linked photocasting service system and method

An improved source/drain junction configuration in a metal-oxide semiconductor transistor is provided, as well as a novel method for fabricating this junction. This configuration employs gate double sidewall spacers in the peripheral region and gate single sidewall spacers in the cell array region. The double sidewall spacers are advantageously formed to suppress the short channel effect, to prevent current leakage, and to reduce sheet resistance. The insulating layer used to form the second spacers in the peripheral region remains in the cell array region and serves as an etching stopper during the etching step of interlayer insulating layer for contact opening formation and also serves as a barrier layer during the step of silicidation formation. As a result the fabrication process of the resulting device is simplified.

Method of fabricating a MOS transistor with double sidewall spacers in a peripheral region and single sidewall spacers in a cell region

A coupling capacitor and a semiconductor memory device using the same are provided. In an embodiment, each memory cell of the semiconductor memory device includes a coupling capacitor so that a storage capacitor can store at least 2 bits of data. The coupling capacitor has a capacitance having a predetermined ratio with respect to the capacitance of the storage capacitor. For this, the coupling capacitor is formed by substantially the same fabrication process as the storage capacitor. The predetermined ratio is obtained by choosing an appropriate number of individual capacitors, each with the same capacitance of the storage capacitor, to comprise the coupling capacitor. Also, the coupling capacitor is disposed on an interlayer insulating layer that buries a bit line in a cell region and a sense amplifier in a sense amplifier region.

Coupling capacitor and semiconductor memory device using the same

A conductive portion connects a lower conductive layer formed on a semiconductor substrate provided in a first interlayer insulating layer to an upper conductive layer formed on the lower conductive layer, and provided in a second interlayer insulating layer. This portion is divided into at least one plug and a pad. At least one plug is formed in a first interlayer insulating layer and the lower part of a second interlayer insulating layer. The second interlayer insulating layer is divided into a plurality of interlayer insulating layers so that upper and lower widths of the divided plugs formed in the divided portion of the second interlayer insulating layer are not greatly different from each other. The pad formed on the upper portion of the second interlayer insulating layer has an upper width such that the upper conductive layer connected to the pad is not undesirably connected to an adjacent upper conductive layer via the pad.

Semiconductor memory device and method for manufacturing the same

An integrated circuit device is manufactured by forming an insulating layer on a substrate. A capping layer is formed on the insulating layer and both the capping layer and the insulating layer are patterned. Insulating spacers are formed on sidewalls of the insulating layer so that the insulating spacers, the capping layer, and the substrate enclose the insulating layer.

Methods of manufacturing integrated circuit devices having an encapsulated insulation layer

An integrated circuit device, e.g., a memory device, includes a substrate, and a plurality of rows of active regions in the substrate, the active regions arranged in a staggered pattern such that active regions of a first row are aligned with portions of an isolation region separating active regions of an adjacent second row. Source and drain regions are in the active regions and are arranged such that each active region comprises a drain region disposed between two source regions. A plurality of word line structures are on the substrate, arranged transverse to the rows of active regions such that that word line structures cross the active regions between the source regions and the drain regions. Respective rows of conductive pads are disposed between respective adjacent word lines structures, including first conductive pads on the source regions, second conductive pads on the drain regions, and third conductive on isolation regions separating active regions. A plurality of bit line structures are on the substrate, extending transverse to the word line structures and contacting the second conductive pads. Related methods of fabrication are also described.

Methods of fabricating integrated circuit devices including self-aligned contacts with increased alignment margin

An integrated circuit device structure which avoids misalignment when a contact hole is formed to expose a contact pad and a method of fabricating the same, are provided. The integrated circuit device includes a semiconductor substrate having a conductive region and an insulating region, a contact pad on the conductive region of the semiconductor substrate, an auxiliary pad adjacent to the contact pad, and an interlevel insulating layer on the semiconductor substrate and having a contact hole for exposing both the contact pad and the auxiliary pad.

Integrated circuit devices with an auxiliary pad for contact hole alignment

Integrated circuit devices including self-aligned contacts with increased alignment margin

A semiconductor memory device from which a floating body effect is eliminated and which has enhanced immunity to external noise, and a method of fabricating the same are provided. The memory device includes a semiconductor substrate. A plurality of bit lines are buried in the semiconductor substrate such that the surfaces of the bit lines are adjacent to the surface of the semiconductor substrate. The bit lines are arranged in parallel with one another. A plurality of word lines are formed on the semiconductor substrate so that the word lines cross and are isolated from the bit lines. A plurality of vertical access transistors are formed at individual memory cells where the bit lines and the word lines intersect. Each vertical access transistor includes a first source/drain region, a body region including a vertical channel region and a second source/drain region which are formed sequentially on the bit line. The vertical access transistor contacts a gate insulation layer formed on a portion of one side of the sidewalls of the word line. Body regions including the channel regions of the access transistors are connected to one another to be a single integrated region.

Semiconductor memory device for eliminating floating body effect and method of fabricating the same

Methods of fabricating integrated circuit devices with contact hole alignment

A resistor which have a stable resistance value and a method for fabricating the same without increasing the area of a semiconductor integrated circuit. To prevent a dishing phenomenon, the resistor is formed on the dummy gate electrode structure which have been formed in a peripheral circuit region and/or it is formed between a pair of dummy bit line structures. Regardless of a process condition the width and height of the resistor can be determined in a certain range with use of the capping layer and spacers of the dummy gate electrode structure and/or the capping layer and/or spacers of the dummy bit line structure.

Growing community of inventors

Kyungki-do, South Korea

Won-Suk Yang