Synopsys, Inc.

Maspar Computer Corporation

Won Sub Kim

Daniel Marcos Chapiro

John R Nickolls

Mary Lynn Meyer

John Zapisek

W Thomas Blank

Kevin Van Horn

Sandro Hermann Pintz

Jeffrey C Kalb

William T Blank

John Harold Downey

David M Bulfer

Valeria Maria Bertacco

Jeffery C Kalb

Hannes Figel

Capabilities are added to a Hardware Verification Language that facilitates the generation of test data. Random number sources, called random variables, can be produced by adding a randomness attribute to a variable declaration of a class definition. A 'randomize' method call to a class instance produces a random value for each random variable. Constraint blocks, of a class definition, control random variables with constraint expressions. Dependency, of random variable value assignment, as determined by constraint expressions, can be expressed by a DAG. A constraint expression is converted into ranges of permissible values, from which a value is randomly chosen by a randomize method. A 'boundary' method call sequentially selects a combination of boundary values, for each random variable, from each random variable's set of ranges. Coordinated selection of a boundary values permits all combinations of boundary values to be produced through successive boundary calls.

Method and apparatus for random stimulus generation

The present invention adds capabilities to a Hardware Verification Language (HVL) which facilitate the generation of random test data. Sources of random numbers are easily produced by simply adding a randomness attribute to a variable declaration of a class definition. Such variables are called random variables. A &ldquo;randomize&rdquo; method call may be made to an instance of the class definition to produce random values for each random variable. The values assigned to random variables are controlled using constraint blocks, which are part of the class definition. A constraint block is comprised of constraint expressions. The constraint expressions may impose a linear ordering in which random variable values must be assigned and this dependency is expressed by directed acyclic graphs (DAGs). The constraint expressions constraining each random variable are converted into ranges of permissible values from which a value is chosen at random. Rather than selecting a value for each random variable from within one of its ranges, as done for the randomize method, each boundary method call sequentially selects a combination of boundary values, for each random variable, from each random variable's set of ranges. By selecting a boundary value for each random variable of the instance, in a coordinated fashion, all combinations of boundary values can be produced through successive calls to the boundary function. As with the randomize method, since random variables may depend upon each other, the selection of a boundary value for one random variable may change the selection of boundary values available for other random variables.

The present invention adds capabilities to a Hardware Verification Language (HVL) which facilitate the generation of random test data. Sources of random numbers are easily produced by simply adding a randomness attribute to a variable declaration of a class definition. Such variables are called random variables. A &ldquo;randomize&rdquo; method call may be made to an instance of the class definition to produce random values for each random variable. The values assigned to random variables are controlled using constraint blocks, which are part of the class definition. A constraint block is comprised of constraint expressions, where each constraint expression limits the values that can be assigned to a random variable on the left-hand-side (lhs) of the constraint expression. If a constraint block of an instance is active or ON, then all the constraint expressions in the block will act to constrain their lhs random variable. A constraint block which is OFF means that all of its constraint expressions will not act to constrain their random variables. The method &ldquo;constraint_mode&rdquo; can be used to turn ON or OFF any constraint blocks of an instance.

The present invention adds capabilities to a Hardware Verification Language (HVL) which facilitate the generation of random test data. Sources of random numbers are easily produced by simply adding a randomness attribute to a variable declaration of a class definition. Such variables are called random variables. A &ldquo;randomize&rdquo; method call may be made to an instance of the class definition to produce random values for each random variable. The values assigned to random variables are controlled using constraint blocks, which are part of the class definition. A constraint block is comprised of constraint expressions, where each constraint expression limits the values that can be assigned to a random variable on the left-hand-side (lhs) of the constraint expression. A constraint_expression can constrain any random variable which has been declared at its level in the class hierarchy, or at any higher level. A constraint_expression cannot constrain a random variable declared at a lower level in the hierarchy. If a constraint block of an instance is active or ON, then all the constraint expressions in the block will act to constrain their lhs random variable. A constraint block which is OFF means that all of its constraint expressions will not act to constrain their random variables. The method &ldquo;constraint_mode&rdquo; can be used to turn ON or OFF any constraint blocks of an instance. The effects of a constraint block can be completely eliminated by defining, at a lower level in the hierarchy, another constraint block with the same name.

Hardware Verification Languages (HVLs) permit the convenient modeling of the environment for a device under test (DUT). HVLs permit the DUT to be tested by stimulating certain inputs of the DUT and monitoring the resulting states of the DUT. The present invention relates to an HVL, referred to as Vera, for the verification of any form of digital circuit design. Vera is preferably used for testing a DUT modeled in a high-level hardware description language (HLHDL) such as Verilog HDL. More specifically, the present invention relates to an HVL capability, know as an &ldquo;expect,&rdquo; for monitoring the values at certain nodes of the DUT at certain times and for determining whether those values are in accordance with the DUT's expected performance. In particular, upon the first occurrence of a transition on one of the DUT's nodes, since beginning a window period of monitoring, the expect will either generate an error if the DUT's output is unexpected, or proceed with modeling the DUT's environment if the output is expected. A delay may be specified, which will delay the expect's initiation of the window monitoring period.

Method and apparatus for determining expected values during circuit design verification

The present invention adds capabilities to a Hardware Verification Language (HVL) which facilitate the generation of random test data. Sources of random numbers are easily produced by simply adding a randomness attribute to a variable declaration of a class definition. Such variables are called random variables. A &ldquo;randomize&rdquo; method call may be made to an instance of the class definition to produce random values for each random variable. The values assigned to random variables are controlled using constraint blocks, which are part of the class definition. A constraint block is comprised of constraint expressions, where each constraint expression limits the values that can be assigned to a random variable on the left-hand-side (lhs) of the constraint expression. Because random variables may also appear on the right-hand-side (rhs) of a constraint expression there is an ordering in which random variable values must be assigned and this dependency is expressed by directed acyclic graphs (DAGs). A linear ordering for assigning values to the random variables is derived from the DAGs. The constraint expressions constraining each random variable are converted into ranges of permissible values from which a value is chosen at random.

The present invention adds capabilities to a Hardware Verification Language (HVL) which facilitate the monitoring of a device under test (DUT). The HVL language supports Object-Oriented Programming (or OOP). Within this OOP framework, the present invention provides a monitoring facility comprised of three main stages: i) Coverage Definitions, ii) Coverage Instantiation and Triggering and iii) Coverage Feedback. A coverage definition is very similar to an OOP class definition, but does not contain methods or variables. Instead, the basic purpose of a coverage definition is to declare &ldquo;monitor bins&rdquo; in terms of a state variable. Essentially, each monitor bin declaration has a unique bin name which is associated with a particular behavior of the state variable and the unique bin name is used to record the state variable's behavior. Instantiation of a coverage definition produces a coverage instance. Two key instantiation parameters are: an actual state variable that is to be monitored by the instance and a trigger expression which determines when the state variable of the instance is to be monitored. Instantiating means that a concurrent, non-terminating, &ldquo;coverage instance process&rdquo; is also forked off. The &ldquo;foreground&rdquo; thread of control which forked off the coverage instance process may continue to operate and subject a DUT to stimuli. The DUT's responses to such stimuli may be monitored by the coverage instance process and stored as data associated with the coverage instance. The same foreground thread of control subjecting the DUT to stimuli can also query the resulting state of the coverage instance's data. This ability to query a coverage instance's data make possible &ldquo;closed loop&rdquo; testing since the foreground thread of control can subsequently alter further stimuli generated for the DUT based upon the results of its query.

Method and apparatus for adaptive verification of circuit designs

A massively parallel computer system is disclosed having a global router network in which pipeline registers are spatially distributed to increase the messaging speed of the global router network. The global router network includes an expansion tap for processor to I/O messaging so that I/O messaging bandwidth matches interprocessor messaging bandwidth. A route-opening message packet includes protocol bits which are treated homogeneously with steering bits. The route-opening packet further includes redundant address bits for imparting a multiple-crossbars personality to router chips within the global router network. A structure and method for spatially supporting the processors of the massively parallel system and the global router network are also disclosed.

Scalable processor to processor and processor to I/O interconnection

A massively parallel processor is provided with a plurality of clusters. Each cluster includes a plurality of processor elements ('PEs') and a cluster memory. Each PE of the cluster has associated with it an address register, a stage register, an error register, a PE enable flag, a memory flag, and a grant request flag. A cluster data bus and an error bus connects each of the stage registers and error registers of the cluster to the memory. The grant request flags of the cluster are interconnected by a polling network, which polls only one of the grant request flags at a time. In response to a signal on the polling network and the state of the associated memory flag, the grant request flag determines an I/O operation between the associated data register and the cluster memory over the cluster data bus. Both data and error bits are associated with respective processor elements. The sequential memory operations proceed in parallel with parallel processor operations. The sequential memory operations also may be queued. Addressing modes include direct and indirect. In direct address mode, a PE addresses its own address space by appending its PE number to a broadcast partial address. The broadcast partial address is furnished over a broadcast bus, and the PE number is furnished on a cluster address bus. In indirect address mode, a PE addresses either its own address space or that of other PEs in its cluster by locally calculating a partial address, then appending to it either its own PE number or that of another PE in its cluster. The full address is furnished over the cluster address bus.

Parallel processor memory transfer system using parallel transfers

A parallel processor system which operates in a single-instruction multiple-data mode has a highly flexible local control capability for enabling the system to operate fast. The system contains an array of processing elements or PEs (12.sub.1 -12.sub.N) that process respective sets of data according to instructions supplied from a global control unit (20). Each instruction is furnished simultaneously to all the PEs. One local control feature (52) entails selectively inverting certain instruction signals according to a data-dependent signal. Another local control feature (48) involves controlling the amount of a bit shift in a barrel shifter (98) according to a data-dependent signal.

Parallel processor system with highly flexible local control capability,

Scalable processor to processor and processor-to-I/O interconnection

A massively parallel processor includes an array of processor elements (20), of PEs, and a multi-stage router interconnection network (30), which is used both for I/O communications and for PE to PE communications. The I/O system (10) for the massively parallel processor is based on a globally shared addressable I/O RAM buffer memory (50) that has address and data buses (52) to the I/O devices (80, 82) and other address and data buses (42) which are coupled to a router I/O element array (40). The router I/O element array is in turn coupled to the router ports (e.g. S2.sub.-- 0.sub.-- X0) of the second stage (430) of the router interconnection network. The router I/O array provides the corner turn conversion between the massive array of router lines (32) and the relatively few buses (52) to the I/O devices.

Growing community of inventors

Fremont, CA, United States of America

Won Sub Kim