Hynix Semiconductor Inc.

Won Sic Woo

Nam-Kyeong Kim

Kyung Pil Hwang

Hee Youl Lee

Ki Hong Lee

Jung Ryul Ahn

Eun Seok Choi

Se Jun Kim

Ki Seon Park

Hyun Seung Yoo

Young Ok Hong

Moon Sig Joo

Kyoung Hwan Park

Myung Shik Lee

Yong Top Kim

Jae Young Park

A method for fabricating a NAND type flash memory device includes defining a select transistor region and a memory cell region in a semiconductor substrate, forming a tunnel insulating layer, a floating gate conductive layer, and a dielectric layer over a semiconductor substrate, etching the dielectric layer, thereby forming an opening exposing the floating gate conductive layer, forming a low resistance layer in the opening, forming a control gate conductive layer over the semiconductor substrate, and etching the control gate conductive layer, the dielectric layer, the floating gate conductive layer, and the tunnel insulating layer to form gate stacks of memory cells and source/drain select transistors.

Method for forming NAND typed memory device

A method of forming the conductive lines of a semiconductor memory device comprises forming a first polysilicon layer over an underlying layer, forming first polysilicon patterns by patterning the first polysilicon layer, filling the space between the first polysilicon patterns with an insulating layer, etching a top portion of the first polysilicon patterns to form recess regions, forming spacers on the sidewalls of the recess regions, filling the recess regions with a second polysilicon layer to form second polysilicon patterns, and performing a metal silicidation process to convert the second polysilicon patterns to metal silicide patterns.

Method of forming conductive lines of semiconductor memory device

A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.

Nonvolatile memory device and method of fabricating the same

Nand type non-volatile memory device and method for fabricating the same

An operation of a non-volatile memory device. A method of operating a non-volatile memory device in accordance with an aspect of the present invention, a first program operation is performed by applying a first program voltage to word lines of memory cells, constituting a memory block. As a result of the first program operation, threshold voltages of the memory cells are firstly measured. A second program operation is performed using a second program voltage, which is increased as much as a difference between a first threshold voltage, that is, a lowest voltage level of the firstly measured threshold voltages and a second threshold voltage, that is, an intermediate voltage level of the firstly measured threshold voltages. The second program operation is repeatedly performed by increasing the second program voltage as much as the difference between the first and second threshold voltages until the lowest threshold voltage becomes higher than a program verify voltage. A pass voltage is then set by reflecting a first voltage level, that is, a difference between a program voltage applied in a last program execution step and the first program voltage.

Method of operating non-volatile memory device

A non-volatile memory device is provided. In an aspect, the non-volatile memory device includes two or more common source lines that are included in one memory cell block in order to distribute the current that could have been concentrated on one common source line. As a result, the bouncing phenomenon generated by the nose of the source line can be reduced. That is, at the time of a verifying operation performed during a program operation, the current concentrated on a common source line can be distributed and, therefore, the occurrence of under-programmed cells can be prevented.

Non-volatile memory device

The present invention relates to a method of manufacturing a semiconductor device. The method comprises the steps of forming a plurality of lower bit lines arranged in a first direction on a semiconductor substrate by performing ion implantation using a mask defining the lower bit lines, forming a lower field oxide film within a region in which the lower bit lines are formed to define an active region and a device isolation region, forming a first insulating film for accumulating charges on the active region, forming a plurality of word lines arranged in parallel in a second direction orthogonal to the first direction of the lower bit lines, depositing an oxide film on the entire structure of the semiconductor substrate including the lower bit lines and the word lines, flattening the oxide film and then removing the oxide film on the word lines, forming a second insulating film for accumulating charges corresponding to the first insulating film for accumulating charges on the word lines and then forming an upper field oxide film corresponding to the lower field oxide film on the word lines, depositing polysilicon on the entire structure of the semiconductor substrate, performing ion implantation using a mask defining upper bit lines for polysilicon to form the upper bit lines, and then performing ion implantation using a mask defining an upper substrate to form the upper substrate, and removing given portions of the upper bit lines formed on the upper field oxide film to separate the upper bit lines.

Method for manufacturing semiconductor device and the device thereof

The present invention relates to a method of manufacturing a NAND flash memory device. Drain select transistors, source select transistors and memory cells are formed in a cell region. After forming peri-transistors in a peripheral circuit region, a metal contact process for electrically connecting them is performed. Upon the metal contact process, the common source line connecting a source region of each of the source select transistors is formed, by patterning the interlayer insulating film to expose the source regions, removing the isolation films between respective source regions to form a common source line contact hole, forming an ion implantation region in the semiconductor substrate at the bottom of the common source line contact hole by means of an ion implantation process, forming a conductive layer so that the common source line contact hole is filled, and blanket-etching the interlayer insulating film as well as the conductive layer by a given thickness. The common source line has a reduced electrical resistance that much since the conductive layer is buried into the removed portion of the isolation film as well as the impurity region formed by the ion implantation process. Due to this, the height of the interlayer insulating film relating to the resistance of the common source line can be lowered. As a result, the aspect ratio is reduced to facilitate a subsequent contact process.

Growing community of inventors

Guri-si, South Korea

Won Sic Woo