Samsung Electronics Co., Ltd.

Won-Seok Jung

Kyungjoong Joo

Chang-seok Kang

Jung-Dal Choi

Sang-Hun Jeon

Changseok Kang

Jin-Taek Park

Seungwoo Paek

Inseok Yang

Jihye Kim

Jaehan Lee

Woong-hee Sohn

Jin-taek Park

Hye-Young Kim

Jongmyeong Lee

Jiwoon Im

Kyung-Tae Jang

Wooseok Chang

Tae-Jong Han

Kwangchul Park

Youngok Kim

Jongwan Choi

Hyoung-Jin Yun

Byungho Chun

Jiyoun Seo

Min-Yong Lee

Sang-Woo Jin

Kyoung-Back Lee

A method for fabricating a semiconductor device includes forming a stacked structure on a substrate, forming a first interlayer dielectric covering the stacked structure, and forming a second interlayer dielectric covering the first interlayer dielectric. The stacked structure includes a stepwise shape. The first interlayer dielectric includes at least one step portion having a slope surface connecting a first top surface to a second top surface. The first top surface and the sloped surface define a first angle that is an obtuse angle. A level of the second top surface is higher than a level of the first top surface.

Method for fabricating semiconductor device including a first ILD with sloped surface on a stacked structure and a second ILD on the first ILD

Provided are semiconductor devices and methods of fabricating the same. The semiconductor devices may include a substrate with a cell region and a peripheral region, a gate stack including gates stacked on the cell region of the substrate. At least one edge portion of the gate stack may have a staircase structure. The semiconductor devices may also include a channel that extend through the gate stack and is enclosed by a memory layer and at least two dummy patterns on the substrate. The at least two dummy patterns may be spaced apart from the gate stack and may be spaced apart from each other.

Semiconductor devices having dummy patterns and methods of fabricating the same

A semiconductor device includes a substrate, a stack structure, peripheral gate structures and residual spacers. The substrate includes a cell array region and a peripheral circuit region. The stack structure is disposed on the cell array region, having electrodes and insulating layers alternately stacked. The peripheral gate structures are disposed on the peripheral circuit region, being spaced apart from each other in one direction and having a peripheral gate pattern disposed on the substrate, and a peripheral gate spacer disposed on a sidewall of the peripheral gate pattern. The residual spacers are disposed on sidewalls of the peripheral gate structures, having a sacrificial pattern and an insulating pattern that are stacked. The insulating pattern includes substantially the same material as the insulating layers of the stack structure.

Semiconductor device and method of fabricating the same

Semiconductor device and method for fabricating the same

A vertical memory device and a method of manufacturing a vertical memory device are disclosed. The vertical memory device includes a substrate, a plurality of channels, a charge storage structure, a plurality of gate electrodes, a first semiconductor structure, and a protection layer pattern. The substrate includes a first region and a second region. The plurality of channels is disposed in the first region. The plurality of channels extends in a first direction substantially perpendicular to a top surface of the substrate. The charge storage structure is disposed on a sidewall of each channel. The plurality of gate electrodes is arranged on a sidewall of the charge storage structure and is spaced apart from each other in the first direction. The first semiconductor structure is disposed in the second region. The protection layer pattern covers the first semiconductor structure. The protection layer pattern has a thickness substantially similar to a thickness of a lowermost gate electrode.

Vertical memory devices and methods of manufacturing the same

A semiconductor memory device may include stacks arranged in a first direction and vertical channel structures provided through the stacks. Each of the stacks may include gate electrodes and insulating layers alternately stacked on a substrate. Each of the vertical channel structures may include a semiconductor pattern connected to the substrate and a vertical channel pattern connected to the semiconductor pattern. Each of the semiconductor patterns may have a recessed sidewall, and the semiconductor patterns may have minimum widths different from each other.

Semiconductor memory devices and methods of fabricating the same

Provided are a multi-process device and an inter-process communication (IPC) method thereof. The multi-processor device includes a first processor, a second processor, a first memory connected to the first processor, and a second memory connected to the second processor. When an inter-process communication (IPC) operation is performed between the first processor and the second processor, data is exchanged between the first memory and the second memory.

Multi-processor device and inter-process communication method thereof

A controller for processing a command in a data storage device includes at least one bitmap and a firmware command que. The at least one bitmap is formed in hardware to indicate that the command is received. The firmware command que is generated by firmware for storing the command when the at least one bitmap indicates receipt of the command. The firmware generates the firmware command que that is of variable size for processing a high number of commands. In addition, the bitmaps are generated in the hardware for quickly receiving the high number of commands.

Method and controller for processing commands in a storage device

Provided are nonvolatile memory devices and methods of forming nonvolatile memory devices. Nonvolatile memory devices include a device isolation layer that defines an active region in a substrate. Nonvolatile memory devices further include a first insulating layer, a nonconductive charge storage pattern, a second insulating layer and a control gate line that are sequentially disposed on the active region. The charge storage pattern includes a horizontal portion and a protrusion disposed on an upper portion of an edge of the horizontal portion.

Nonvolatile memory devices and methods of forming the same

A semiconductor device includes a device isolation layer in a semiconductor substrate, an active region defined by the device isolation layer, the active region including a main surface and a recess region including a bottom surface that is lower than the main surface, and a gate electrode formed over the recess region, wherein a top surface of the device isolation layer adjacent to the recess region is lower than the bottom surface of the recess region.

Semiconductor devices and methods of fabricating the same

A nonvolatile memory device includes a semiconductor substrate including a cell region and a peripheral circuit region, a cell gate on the cell region, and a peripheral circuit gate on the peripheral circuit region, wherein the cell gate includes a charge storage insulating layer on the semiconductor substrate, a gate electrode on the charge storage insulating layer, and a conductive layer on the gate electrode, and the peripheral circuit gate includes a gate insulating layer on the semiconductor substrate, a semiconductor layer on the gate insulating layer, an ohmic layer on the semiconductor layer, and the conductive layer on the ohmic layer.

Nonvolatile memory devices and methods of fabricating the same

A track cross signal correction apparatus removes noise components contained in a track cross signal. The apparatus includes mask signal generator for comparing pulse widths of the received track cross signals with threshold values, based on the pulse width of a previous track cross signal. A mask signal is generated according to the comparison result. A corrector outputs a received track cross signal when mask signals are generated from the mask signal generator. The track cross signal correction apparatus accurately performs a track seek operation in a medium such as a CD-ROM which requires high-speed access.

Growing community of inventors

Anyang-si, South Korea

Won-Seok Jung