Skhynix Inc.

Won-Seok Hwang

Si-Wook Yoo

Sung-Jin Lee

An image sensing device includes a pixel array; a plurality of lines coupled to the pixel array; a readout circuit coupled to the plurality of lines and structured to output a readout reset signal and a readout data; first readout lines coupled to the readout circuit and structured to transfer readout reset signals and readout data signals; a global counter coupled to count the readout reset signals and the readout data signals; a first storing circuit coupled to the first readout lines to receive the readout reset signals and the readout data signals; a line control circuit coupled to the first storing circuit; second readout lines coupled to the line control circuit and structured to transfer the readout control signals received from the line control circuit; and a second storing circuit coupled to the second readout lines to receive the readout control signals.

Image sensing device

An image sensing device includes: a pixel array suitable for generating a plurality of pixel signals corresponding to incident light; a comparison block suitable for comparing the pixel signals with a ramp signal to generate a plurality of comparison signals; a logic block suitable for adjusting slew rates of the respective comparison signals to generate a plurality of logic signals; a global count block suitable for generating a global count signal; and a storing block suitable for storing counted values of the global count signal based on the logic signals received from the logic block.

Image sensing device and method for driving the same

Disclosed are a latch circuit receiving a negative output of a next stage latch circuit as a feedback input, a double data rate (DDR) ring counter based on the latch circuit to perform DDR counting of pulse periods and reduce the number of toggles, a hybrid counting device counting lower-bit portion by using the latch-based DDR ring counter and upper-bit portion by using a binary counter, and an analog-to-digital converting device and a CMOS image sensor employing the hybrid counting device. A double data rate ring counter may include a plurality of latches coupled in a ring type. The plurality of latches may include positive-edge-triggered latches and negative-edge-triggered latches arranged alternately. A current stage latch receives an output of a previous latch stage to shift to a next latch stage according to a counter clock, receives an output of the next latch stage to check a data shift to the next latch stage, and falls to a low level if the data shift is checked.

Latch circuit, double data rate ring counter based on the latch circuit, hybrid counting device, analog-digital converting device, and CMOS image sensor

A count circuit includes a count block suitable for generating count code signals for a predetermined count period including a first period and a second period; and a storage block suitable for storing first bit signals among a plurality of bit signals included in the count code signals, for the first period, and storing remaining bit signals among the plurality of bit signals for the second period.

Count circuit, method for driving count circuit, and image sensor including count circuit

A group selection circuit includes an input block suitable for receiving a last column select signal of a previous column switch group and a last column select signal of a current column switch group; and a group selection block suitable for generating a group select signal that is activated from a first edge of the last column select signal of the previous column switch group to a first edge of the last column select signal of the current column switch group, in response to an output signal of the input block.

Group selection circuit, and column readout device and method thereof

Disclosed are a latch circuit receiving a negative output of a next latch stage circuit as a feedback input, a double data rate (DDR) ring counter based on the latch circuit to perform DDR counting of pulse periods and reduce the number of toggles, a hybrid counting device counting lower-bit portion by using the latch-based DDR ring counter and upper-bit portion by using a binary counter, and an analog-to-digital converting device and a CMOS image sensor employing the hybrid counting device. A double data rate ring counter may include a plurality of latches coupled in a form of a ring. The plurality of latches may include positive-edge-triggered latches and negative-edge-triggered latches arranged alternately. A current latch stage receives an output of a preceding latch stage to shift to a next latch stage according to a counter clock, receives an output of the next latch stage to check a data shift to the next latch stage, and falls to a low level if the data shift is checked.

Double data rate decoding device with edge-triggered shifting latch stages

A counting apparatus that includes a global counting unit suitable for performing a counting operation by controlling a counting bit number based on a count masking signal; a one-shot pulse generation unit suitable for generating a storage instruction signal based on the count masking signal; a latch unit suitable for storing a counting value outputted from the global counting unit based on the storage instruction signal; and a storage unit suitable for storing the counting value loaded from the latch unit.

Counting apparatus and image sensor including the same

A Double Data Rate (DDR) counter includes an input clock control portion suitable for generating a first clock corresponding to a state of a input clock based on a counter enable signal, and an LSB control portion suitable for holding a least significant bit based on the counter enable signal and successively performing a counting operation on the first clock in multiple sections.

Double data rate counter, and analog-to-digital converter and CMOS image sensor using the same

An electronic device includes a control logic portion suitable for generating a hold control signal based on a count enable signal, and a counting portion suitable for performing a counting operation while a latch operation stops during a counting section and performing the latch operation while the counting operation stops during a holding section based on the hold control signal and a counting clock signal.

Electronic device and electronic system including the same

A ramp signal generator may include: a differential amplification unit suitable for generating an amplified signal corresponding to a voltage difference between a reference voltage and a feedback voltage; a driving unit suitable for driving an output terminal of the feedback voltage to a ground voltage in response to the amplified signal, and generating the feedback voltage corresponding to the reference voltage; and a ramp signal generation unit suitable for generating a ramp signal using a ramp supply voltage and the feedback voltage.

Ramp signal generator and image sensor including the same

A counting device includes a control unit suitable for generating a control signal including a first control signal and a second control signal, a first operation unit suitable for performing a logic operation for pixel signals of a pixel array and a control signal, wherein pixel signals of used column in the pixel array are transferred by using the first control signal, and pixel signals of unused column in the pixel array are blocked by using the second control signal during a binning mode operation, a second operation unit suitable for performing a logic operation for a counter clock and an output signal of the first operation unit, and a counting unit suitable for counting an output signal of the second operation unit.

Counting device for reducing power consumption in binning mode and method therefor

A double data rate (DDR) counter includes a clock selection unit suitable for selectively inverting a first counting clock based on a control signal and for outputting a second counting clock, a first latch stage suitable for latching the second counting clock based on a counting enable signal and for outputting the least significant bit (LSB) of the DDR counter, a determination unit suitable for generating the control signal based on the last bit state of the LSB in a reset counting period, and a second latch stage suitable for receiving the LSB as a clock input to generate a higher bit of the LSB at least in a main counting period.

Double data rate counter, and analog-digital converting apparatus and CMOS image sensor using the same

An image sensing device includes a plurality of pixels arranged in rows and columns and a sampling unit suitable for sampling the plurality of pixels in units of M by N in a binning mode, M and N being a positive integer greater than 2.

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Gyeonggi-do, South Korea

Won-Seok Hwang