Samsung Electronics Co., Ltd.

Won-mo Park

Seong-Ho Kim

Gil-Sub Kim

Young-hun Park

Jong-Jin Lee

Ji-hong Ahn

Kyeong-tae Kim

Ho-Ju Song

Jung-hyun Shin

Dong-Kwan Yang

Yun-seung Shin

Hyun-Chul Kim

Min-wk Hwang

A method of fabricating a semiconductor memory device includes preparing a semiconductor substrate which is divided into a cell array region and a core and peripheral region adjacent to the cell array region. Signal lines may be formed in a lower layer in a cell region. An insulation layer may be formed on the lower layer. Signal lines connected to cell region signal lines may be formed on an insulation layer of the peripheral region. A capping layer may be formed on the insulation layer and the core and peripheral signal lines. The capping layer may be etched to expose the lower layer of the cell array region and an etch stop may be formed on the lower layer and the core and peripheral region.

Method of fabricating and semiconductor memory device using the same

A fuse structure, an e-fuse including the fuse structure and a semiconductor device including the e-fuse are disclosed. The fuse structure includes first and second electrodes extending in a first direction, and spaced a predetermined distance apart from each other and having one ends thereof facing each other, an insulation layer formed between the one end of the first electrode and the one end of the second electrode facing each other, and a conductive film overlapping portions of the first and second electrodes on the insulation layer and contacting the first electrode and the one end of the second electrode.

Fuse structures, e-fuses comprising fuse structures, and semiconductor devices comprising e-fuses

A semiconductor device includes a fuse having the form of a capacitor. The semiconductor device includes a cathode formed on a semiconductor substrate, an anode formed over the cathode, and at least one filament having a cylindrical-shell shape formed between the cathode and the anode and electrically connecting the cathode and the anode.

Semiconductor device including fuse having form of capacitor

Provided is a semiconductor memory device including cylinder type storage nodes and a method of fabricating the semiconductor memory device. The semiconductor memory device includes: a semiconductor substrate including switching devices; a recessed insulating layer including storage contact plugs therein, wherein the storage contact plugs are electrically connected to the switching devices and the recessed insulating layer exposes at least some portions of upper surfaces and side surfaces of the storage contact plugs. The semiconductor device further includes cylinder type storage nodes each having a lower electrode. The lower electrode contacting the at least some portions of the exposed upper surfaces and side surfaces of the storage node contact plugs.

Semiconductor memory device including a cylinder type storage node and a method of fabricating the same

A method of forming a semiconductor memory device includes sequentially forming an etch stop layer and then a mold layer, forming a plurality of line-shaped support structures and a first sacrificial layer filling gaps between the support structures on the mold layer, sequentially forming a plurality of line-shaped first mask patterns, a second sacrificial layer, and then second mask patterns on the support structures and on the first sacrificial layer, removing the second sacrificial layer, the first sacrificial layer, and the mold layer using the first mask patterns, the second mask patterns, and the support structures as masks, removing the first mask patterns and second mask patterns, filling the storage node electrode holes with a conductive material and etching back the conductive material to expose the support structures, and removing the first sacrificial layer and the mold layer to form pillar-type storage node electrodes supported by the support structures.

Method of forming capacitor of semiconductor memory device

In a semiconductor device having a capacitor and a method of fabricating the same, the semiconductor device comprises a semiconductor substrate and an insulating layer on the semiconductor substrate, a contact plug electrically connected to the semiconductor substrate and formed in the contact hole, a buffer conductive layer pattern electrically connected to the contact plug and formed on the insulating layer and the contact plug, an etching stopping layer formed on the buffer conductive layer pattern, a gap between the buffer conductive layer pattern and the etching stopping layer, a capacitor lower electrode electrically connected to the buffer conductive layer pattern and formed on the buffer conductive layer pattern. The gap is filled by a portion of the capacitor lower electrode.

Semiconductor device having a capacitor and a fabrication method thereof

A capacitor having a perovskite series dielectric film, and manufacturing method thereof are provided. The perovskite series dielectric film capacitor is characterized in that the perovskite series dielectric film contains copper. The method of manufacturing the perovskite series dielectric film which contains copper includes forming the perovskite series dielectric film on a lower electrode, forming a Cu O film on the perovskite series dielectric film, and permitting Cu O or copper of the Cu O film to penetrate the perovskite series dielectric film preferably by a heat treatment. In the perovskite series dielectric film capacitor, Cu O or copper penetrates the grain boundary of the perovskite series dielectric film having a columnar crystal structure, thereby improving a leakage current characteristic of the perovskite series dielectric film.

Capacitor having perovskite series dielectric film containing copper and manufacturing method thereof

A semiconductor device having a closed step portion and a global step portion including an insulating layer having a planarized surface on the global step portion is provided. A dummy pattern is formed by forming an insulating layer on the global step portion and then patterning through a photolithography process. After forming the dummy pattern for compensating steps in the global step portion and between the closed step portion and the global step portion, a BPSG layer is formed on both the closed step portion and the global step portion, and then the BPSG layer is heat-treated to cause it to reflow. The BPSG layer as an insulating interlayer having a planarized surface. The improved planarization decreases the occurrence of notching and discontinuities in the succeeding metallization processes thereby enhancing the yield and electrical characteristics of the semiconductor device.

Semiconductor device and a method of manufacture

A method for manufacturing a capacitor for a semiconductor device, which includes the steps of forming a first conductive layer on a semiconductor substrate, forming a first pattern by patterning the first conductive layer, sequentially forming a second conductive layer and a first material layer on the entire surface of the resultant structure, forming a spacer on the sidewall of the second conductive layer by anisotropic-etching the first material layer, forming a second pattern by partially etching the second conductive layer and the first pattern, using the spacer as an etching mask, forming a third conductive layer on the entire surface of the resultant structure, forming a cylindrical storage electrode by anisotropic-etching the third conductive layer, and removing the spacer.

Method for manufacturing a capacitor for a semiconductor device

A highly integrated semiconductor device and method for manufacturing the same are disclosed. The device has a self-aligned contact structure for increasing a contact margin upon forming a self-aligned buried contact hole. An oxide film of an upper portion of a gate electrode is chamfered in order to form a self-aligned buried contact hole. Therefore, a self-aligned contact hole can be formed without enhancing the step, and as a result, the step between the cell and the peripheral portion of the cell can be reduced.

Method of manufacturing a semiconductor device having self aligned

Semiconductor device and manufacturing method thereof

A method for manufacturing a semiconductor device having a closed step portion and a global step portion including an insulating layer is provided. A dummy pattern is formed by forming an insulating layer on the global step portion and then patterning through a photolithography process. After forming the dummy pattern for compensating steps in the global step portion and between the closed step portion and the global step portion, a BPSG layer is formed on both the closed step portion and the global step portion, and then the BPSG layer is heat-treated to cause it to reflow. The BPSG layer as an insulating interlayer having a planarized surface. The improved planarization decreases the occurrence of notching and discontinuities in the succeeding metallization processes thereby enhancing the yield and electrical characteristics of the semiconductor device.

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Seongnam-si, South Korea

Won-mo Park